Initial work on rom_sd

This module needs way reworked to just be a state machine. I was trying
to get way too tricky with it so I went back to the drawing board and
made a state machine diagram for it. The diagram is included with this
commit. I also moved the current collection of documentation to a doc/
folder, and added a second-long audio rom to test everything out once
the rom_sd is working.

Nexys-A7-100T-Master.xdc

@@ -5,8 +5,11 @@
 ## Note: As the Nexys 4 DDR was rebranded to the Nexys A7 with no substantial changes, this XDC file will also work for the Nexys 4 DDR.
 
 ## Clock signal
-#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ]
-#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK100MHZ]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
 
 
 ##Switches
@@ -54,31 +57,31 @@
 #set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
 
 ##7 segment display
-#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports CA]
-#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
+set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports CB]
-#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
+set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports CC]
-#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
+set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports CD]
-#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports CE]
-#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports CF]
-#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
+set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports CG]
 #set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
-#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {AN[0]}]
-#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {AN[1]}]
-#set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {AN[2]}]
-#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {AN[3]}]
-#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {AN[4]}]
-#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {AN[5]}]
-#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
+set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {AN[6]}]
-#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {AN[7]}]
 
 ##CPU Reset Button
-#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports CPU_RESETN]
 
 ##Buttons
-#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports BTNC]
 #set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
 #set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
-#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
+set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports BTNR]
 #set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
 
 
@@ -212,3 +215,70 @@
 #set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
 #set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
 #set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list CLK100MHZ_IBUF_BUFG]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 6 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {seconds_reg[0]} {seconds_reg[1]} {seconds_reg[2]} {seconds_reg[3]} {seconds_reg[4]} {seconds_reg[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 6 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {minutes[0]} {minutes[1]} {minutes[2]} {minutes[3]} {minutes[4]} {minutes[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 3 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {playbackController/current[0]} {playbackController/current[1]} {playbackController/current[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 6 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {hours_reg[0]} {hours_reg[1]} {hours_reg[2]} {hours_reg[3]} {hours_reg[4]} {hours_reg[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 3 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {anodeDriver/mux_select[0]} {anodeDriver/mux_select[1]} {anodeDriver/mux_select[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 8 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {AN_OBUF[0]} {AN_OBUF[1]} {AN_OBUF[2]} {AN_OBUF[3]} {AN_OBUF[4]} {AN_OBUF[5]} {AN_OBUF[6]} {AN_OBUF[7]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list CA_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list CB_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list CC_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list CD_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list CE_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list CF_OBUF]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list CG_OBUF]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets CLK100MHZ_IBUF_BUFG]

SDVD.xpr

@@ -43,11 +43,11 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
-    <Option Name="BoardPart" Val="digilentinc.com:nexys-a7-100t:part0:1.2"/>
+    <Option Name="BoardPart" Val=""/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../.Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
     <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
     <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
     <Option Name="IPCachePermission" Val="read"/>
@@ -60,19 +60,19 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="nexys-a7-100t"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="87"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="1"/>
-    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="1"/>
-    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="1"/>
     <Option Name="WTIesExportSim" Val="0"/>
-    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="1"/>
-    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="1"/>
     <Option Name="WTActivehdlExportSim" Val="0"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
@@ -98,6 +98,27 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/design/segment_display/display_anode_driver.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/segment_display/display_converter.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/low_freq_clock_gen.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/design/playback_controller.sv">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -105,7 +126,37 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/design/seconds_display.sv">
+      <File Path="$PPRDIR/design/segment_display/seconds_display.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/nexys_a7_top.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sdvd_defs.sv">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/audio/audio_buffer.sv">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/audio/pwm.sv">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -115,8 +166,9 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="Playback_Controller"/>
+        <Option Name="TopModule" Val="nexys_a7_top"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="VerilogDir" Val="$PPRDIR/design"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -128,14 +180,21 @@
         </FileInfo>
       </File>
       <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/Nexys-A7-100T-Master.xdc"/>
         <Option Name="ConstrsType" Val="XDC"/>
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/debouncer_assertions.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/verification/debouncer_tb.sv">
         <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -143,9 +202,49 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="Playback_Controller"/>
+        <Option Name="TopModule" Val="debouncer_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="seconds_display_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/seconds_display_tb" RelGenDir="$PGENDIR/seconds_display_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/segment_display/seconds_display_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="seconds_display_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -159,10 +258,66 @@
         <Option Name="CosimElf" Val=""/>
       </Config>
     </FileSet>
-    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <FileSet Name="playback_controller_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/playback_controller_tb" RelGenDir="$PGENDIR/playback_controller_tb">
-      <Filter Type="Utils"/>
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/playback_controller_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sdvd_defs.sv">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
-        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="playback_controller_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="VerilogDir" Val="$PPRDIR/design"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+      </Config>
+    </FileSet>
+    <FileSet Name="audio_buffer_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/audio_buffer_tb" RelGenDir="$PGENDIR/audio_buffer_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/audio/audio_buffer_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="audio_buffer_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="10s"/>
       </Config>
     </FileSet>
   </FileSets>
@@ -188,7 +343,7 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
@@ -220,10 +375,266 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="impl_1_copy_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
+        <ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="nexys_a7_top_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="nexys_a7_top_drc_opted.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="nexys_a7_top_timing_summary_opted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="nexys_a7_top_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="nexys_a7_top_io_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="nexys_a7_top_utilization_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="nexys_a7_top_control_sets_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="verbose" Type="" Value="true"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="nexys_a7_top_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="nexys_a7_top_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="nexys_a7_top_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="nexys_a7_top_drc_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="nexys_a7_top_methodology_drc_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="nexys_a7_top_power_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="nexys_a7_top_route_status.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="nexys_a7_top_timing_summary_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="nexys_a7_top_incremental_reuse_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="nexys_a7_top_clock_utilization_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="nexys_a7_top_bus_skew_routed.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+      </ReportStrategy>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1_copy_2" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_2" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_2" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
+        <ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_2_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="nexys_a7_top_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_2_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="nexys_a7_top_drc_opted.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_2_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="nexys_a7_top_timing_summary_opted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_2_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="nexys_a7_top_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_2_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="nexys_a7_top_io_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_2_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="nexys_a7_top_utilization_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_2_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="nexys_a7_top_control_sets_placed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="verbose" Type="" Value="true"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_2_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_2_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_2_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="nexys_a7_top_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_2_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="nexys_a7_top_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_2_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="nexys_a7_top_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_2_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_2_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="nexys_a7_top_drc_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_2_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="nexys_a7_top_methodology_drc_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_2_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="nexys_a7_top_power_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_2_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="nexys_a7_top_route_status.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_2_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="nexys_a7_top_timing_summary_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_2_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="nexys_a7_top_incremental_reuse_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_2_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="nexys_a7_top_clock_utilization_routed.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_2_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="nexys_a7_top_bus_skew_routed.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_2_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_2_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_2_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+      </ReportStrategy>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
-  <Board>
+  <Board/>
-    <Jumpers/>
-  </Board>
   <DashboardSummary Version="1" Minor="0">
     <Dashboards>
       <Dashboard Name="default_dashboard">

design/audio/audio_buffer.sv

@@ -0,0 +1,145 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+
+//this interfaces with block ram
+module audio_buffer(
+    // The clock should be at 48khz
+    input logic clk, reset,
+
+    // Control signals
+    input logic play, stop,
+    input SPEED speed,
+
+
+    // Whether the audio buffer is currently playing
+    output logic playing,
+
+    // A 16-bit audio sample to output
+    output logic [15:0] sample,
+
+    // Inputs for the memory buffer
+    audio_buffer_interface.receiver driver
+);
+
+// Whether the current address being read from is in the upper or lower
+// half of the 2KiB buffer
+let address_half = driver.address_half;
+
+logic [9:0] address;
+
+// State register
+logic enb;
+logic [15:0] doutb;
+
+// A single bit counter, to avoid feeding samples given the 1 cycle read delay
+logic delay;
+
+// The MSB of the address == higher/lower half address
+assign address_half = address[9];
+
+always_ff @(posedge clk) begin
+    enb <= 0;
+    if (reset) begin
+        playing <= 0;
+        address <= 0;
+        sample <= 0;
+        delay <= '1;
+    end
+    else if (!playing) begin
+        if (play) begin
+            playing <= 1;
+            delay <= '1;
+        end
+
+    end
+    else begin
+        if (stop) begin
+            playing <= 0;
+            // If playback "Stops" then reset the address to a known value, 0
+            address <= 0;
+            delay <= '1;
+        end
+        else begin
+            // This will overflow to the correct value always
+            address <= address + speed;
+            enb <= 1;
+            // NOTE: I really don't know a good way to generate the load
+            // signal. It maybe could be an inverted 48khz clock?
+            if (delay == 0) begin
+                sample <= doutb;
+            end
+            else begin
+                sample <= '0;
+                delay <= '0;
+            end
+            
+        end
+    end
+end
+
+//xpm_memory_sdpram #(
+//    .WRITE_DATA_WIDTH_A(16)
+//) buffer ();
+xpm_memory_sdpram #(
+  .ADDR_WIDTH_A(11),               // DECIMAL
+  .ADDR_WIDTH_B(10),               // DECIMAL
+  .AUTO_SLEEP_TIME(0),            // DECIMAL
+  .BYTE_WRITE_WIDTH_A(8),        // DECIMAL
+  .CASCADE_HEIGHT(0),             // DECIMAL
+  .CLOCKING_MODE("independent_clock"), // String
+  .ECC_BIT_RANGE("7:0"),          // String
+  .ECC_MODE("no_ecc"),            // String
+  .ECC_TYPE("none"),              // String
+  .IGNORE_INIT_SYNTH(0),          // DECIMAL
+  .MEMORY_INIT_FILE("none"),      // String
+  .MEMORY_INIT_PARAM("0"),        // String
+  .MEMORY_OPTIMIZATION("true"),   // String
+  .MEMORY_PRIMITIVE("auto"),      // String
+  .MEMORY_SIZE(16*1024),             // DECIMAL
+  .MESSAGE_CONTROL(0),            // DECIMAL
+  .RAM_DECOMP("auto"),            // String
+  .READ_DATA_WIDTH_B(16),         // DECIMAL
+  .READ_LATENCY_B(1),             // DECIMAL
+  .READ_RESET_VALUE_B("0"),       // String
+  .RST_MODE_A("SYNC"),            // String
+  .RST_MODE_B("SYNC"),            // String
+  .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL
+  .USE_MEM_INIT(1),               // DECIMAL
+  .USE_MEM_INIT_MMI(0),           // DECIMAL
+  .WAKEUP_TIME("disable_sleep"),  // String
+  .WRITE_DATA_WIDTH_A(8),        // DECIMAL
+  .WRITE_MODE_B("no_change"),     // String
+  .WRITE_PROTECT(1)               // DECIMAL
+)
+buffer (
+  .doutb(doutb),          // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
+  .addra(driver.addra),          // ADDR_WIDTH_A-bit input: Address for port A write operations.
+  .addrb(address),        // ADDR_WIDTH_B-bit input: Address for port B read operations.
+  .clka(driver.clka),            // 1-bit input: Clock signal for port A. Also clocks port B when
+                          // parameter CLOCKING_MODE is "common_clock".
+
+  .clkb(clk),             // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
+                          // "independent_clock". Unused when parameter CLOCKING_MODE is
+                          // "common_clock".
+  .dina(driver.dina),            // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+  .ena(driver.ena),              // 1-bit input: Memory enable signal for port A. Must be high on clock
+                          // cycles when write operations are initiated. Pipelined internally.
+
+  .enb(enb),              // 1-bit input: Memory enable signal for port B. Must be high on clock
+                          // cycles when read operations are initiated. Pipelined internally.
+//active high reset
+  .rstb(reset),            // 1-bit input: Reset signal for the final port B output register stage.
+                          // Synchronously resets output port doutb to the value specified by
+                          // parameter READ_RESET_VALUE_B.
+  .wea(driver.ena)               // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+                          // for port A input data port dina. 1 bit wide when word-wide writes are
+                          // used. In byte-wide write configurations, each bit controls the
+                          // writing one byte of dina to address addra. For example, to
+                          // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
+                          // is 32, wea would be 4'b0010.
+);
+
+endmodule

design/audio/pwm.sv

@@ -0,0 +1,49 @@
+/****
+ * pwm.sv - [must edit in future]
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: [not sure when due yet]
+ *
+ *
+ * */
+module pwm(
+    input logic clk, reset,
+    // Load control signal, if this is high we should load a new sample
+    input logic load,
+    // The audio sample to play back
+    input logic [15:0] sample,
+    // The audio output pin
+    output wire pwm_pin
+);
+
+logic [15:0] pulse_counter;
+logic [15:0] sample_buffer;
+logic should_output;
+
+always_ff @(posedge clk)
+begin
+    if (reset)
+    begin
+        pulse_counter <= 0;
+        sample_buffer <= 0;
+    end
+    
+    else
+    begin
+        if (load)
+            sample_buffer <= sample;
+        
+        pulse_counter <= pulse_counter + 1;
+
+        if (pulse_counter < sample_buffer)
+            should_output <= 1;
+        else
+            should_output <= 0;
+    end
+
+end
+
+assign pwm_pin = should_output ? 'z : '0;
+
+
+endmodule

design/debouncer.sv

@@ -1,23 +1,22 @@
 //NOTE: you should drive this with a slow clock to actually debounce input
-module debouncer(input logic clk, input reset, input source, output wire out);
+module debouncer(input logic clk, input reset, input source, output logic out);
 
 logic pressed;
-assign out = pressed;
 
 always_ff @(posedge clk) begin
     if (reset)
         pressed <= 0;
-    else if (!pressed && source)
+    if (!source) begin
-        pressed <= 1;
-    else if (pressed && !source)
         pressed <= 0;
+        out <= 0;
+    end
+    else
+        if (pressed)
+            out <= 0;
+        else begin
+            pressed <= 1;
+            out <= 1;
+        end
 end
 
-
-//always_ff (@posedge clk) begin
-//
-//end
-
-
-
 endmodule

design/low_freq_clock_gen.sv

@@ -0,0 +1,58 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+// Takes in a 100MHz clock and generates the very low freq signals needed
+// for driving the control logic
+module low_freq_clock_gen(
+    input logic clk, reset,
+    input SPEED speed,
+    output logic clk1k, clk10h, seconds_pulse
+);
+
+// Hardcoded to be 1,000,000/4,000
+// Relying on constant maths makes it the wrong size
+localparam num_cycles = 25_000;
+
+logic [$clog2(num_cycles):0] counter;
+logic [$clog2(4000):0] seconds_counter;
+logic [$clog2(4000):0] clock_divider_counter;
+
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        counter <= num_cycles;
+        clk1k <= 0;
+        clk10h <= 0;
+        seconds_pulse <= 0;
+        seconds_counter <= 0;
+        clock_divider_counter <= 0;
+    end
+    // At 4khz increment the seconds counter and output clocks
+    else if (counter == 0) begin
+        counter <= num_cycles;
+        seconds_counter <= seconds_counter + {9'b0, speed};
+        clock_divider_counter <= clock_divider_counter + 1;
+        if (seconds_counter >= 4000) begin
+            seconds_counter <= seconds_counter-4000;
+            // Should we flop it or pulse at 100MHz?
+            seconds_pulse <= 1;
+        end
+        else
+            seconds_pulse <= 0;
+
+        if (clock_divider_counter == 4000)
+            clock_divider_counter <= 0;
+
+        // Generate output clocks
+        if (clock_divider_counter % 4 == 0)
+            clk1k <= ~clk1k;
+        if (clock_divider_counter % 400 == 0)
+            clk10h <= ~clk10h;
+        end
+    else
+        counter <= counter - 1;
+
+end
+    
+endmodule

design/nexys_a7_top.sv

@@ -0,0 +1,72 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+module nexys_a7_top(
+    input logic CLK100MHZ, CPU_RESETN,
+    input logic BTNC, BTNR,
+    output logic CA,CB,CC,CD,CE,CF,CG,
+    output logic [7:0] AN
+);
+
+// Active high reset
+wire reset;
+assign reset = ~CPU_RESETN;
+
+logic clk_1khz, clk_10hz;
+logic seconds_pulse;
+
+SPEED speed;
+
+// Map C{A-G} to an array of 7-segment displays
+wire [6:0] segments [7:0];
+wire [2:0] segment_mux_select;
+
+// These segments are currently unused
+assign segments[7] = 0;
+assign segments[6] = 0;
+assign {CA,CB,CC,CD,CE,CF,CG} = ~segments[segment_mux_select];
+
+logic [$clog2(60)-1:0] seconds;
+logic [$clog2(60)-1:0] minutes;
+logic [$clog2(60)-1:0] hours;
+
+low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
+
+// Count the number on seconds, hours, and minutes elapsed
+// If the speed is faster this will pulse more often than once a second
+// but will still theoretically be a second of video time
+always_ff @(posedge seconds_pulse) begin
+    if (reset) begin
+        seconds <= 0;
+        minutes <= 0;
+        hours <= 0;
+    end
+    else if (seconds == 59) begin
+        seconds <= 0;
+        if (minutes == 59) begin
+            minutes <= 0;
+            hours <= hours + 1;
+        end
+        else
+            minutes <= minutes + 1;
+    end
+    else
+        seconds <= seconds + 1;
+end
+
+display_anode_driver anodeDriver(clk_1khz,reset,AN,segment_mux_select);
+
+seconds_display secondsSegment (seconds, segments[1], segments[0]);
+seconds_display minutesSegment (minutes, segments[3], segments[2]);
+seconds_display hoursSegment (hours, segments[5], segments[4]);
+
+// Run the playback speed state machine at a lower rate
+// Gets rid of button bouncing
+playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
+
+
+
+
+
+endmodule

design/playback_controller.sv

@@ -1,4 +1,20 @@
-module Playback_Controller(
+/*****
+ * playback_controller.sv - A finite state machine with states that control
+ *                          playback speed. In additon to playing and pausing
+ *                          it can fast forward at 2x speed, 4x speed, 8x
+ *                          speed and 16x speed.
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/25
+ *
+ * */
+
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+
+module playback_controller(
     // This clock should be reasonably slow
     input logic clk,
     input logic reset,
@@ -7,14 +23,90 @@ module Playback_Controller(
     input logic play,
     input logic ff,
 
-    // Output is 0, 1x, 2x, 4x, or 8x
+    // Output is 0, 1x, 2x, 4x, 8x or 16x
-    output wire [3:0] speed
+    output SPEED speed
 );
 
+typedef enum logic [2:0] {
+    PAUSE, PLAY, FF2, FF4, FF8, FF16
+} state_t;
+
+state_t current, next;
+
 wire play_pulse,ff_pulse;
 
 // NOTE: These might need to be hooked to an even lower clock? Not sure
 debouncer playDebouncer (clk,reset,play,play_pulse);
 debouncer ffDebouncer (clk,reset,ff,ff_pulse);
 
+//next state logic
+always_comb
+begin
+    unique case (current)
+        PAUSE: 
+            begin
+                if (play_pulse) next = PLAY;
+                else if (ff_pulse) next = FF2;
+                else next = PAUSE;
+            end
+        PLAY: 
+            begin
+                if (play_pulse) next = PAUSE;
+                else if (ff_pulse) next = FF2;
+                else next = PLAY;
+            end
+        FF2:
+            begin
+                if (play_pulse) next = PAUSE;
+                else if (ff_pulse) next = FF4;
+                else next = FF2;
+            end
+        FF4:
+            begin
+                if (play_pulse) next = PAUSE;
+                else if (ff_pulse) next = FF8;
+                else next = FF4;
+            end
+        FF8:
+            begin
+                if (play_pulse) next = PAUSE;
+                else if (ff_pulse) next = FF16;
+                else next = FF8;
+            end
+        FF16:
+            begin
+                if (play_pulse) next = PAUSE;
+                else if (ff_pulse) next = FF16;
+                else next = FF16;
+            end
+        default:
+            next = PAUSE;
+    endcase
+end
+
+//output logic
+always_comb
+begin
+    unique case (current)
+        PAUSE:  speed = 0; 
+        PLAY:   speed = 1;
+        FF2:    speed = 2;
+        FF4:    speed = 4;
+        FF8:    speed = 8;
+        FF16:   speed = 16;
+        default:speed = 0;
+    endcase
+end
+
+//sequential logic
+always_ff @(posedge clk)
+begin    
+    if (reset)
+        current <= PAUSE;
+    else
+        current <= next;
+end
 endmodule
+
+
+

design/sd/rom_sd.sv

@@ -0,0 +1,103 @@
+// A dummy sdcard module for testing the audio port
+
+module sd(
+    input logic clk,
+    input logic reset,
+    output logic ready,
+
+    audio_buffer_interface.driver audio_buffer
+);
+
+// First we write 2048B into the memory buffer, then signal to play it and
+// wait for half signal to avoid overwriting memory
+logic initializing;
+logic [16:0] rom_address;
+logic [7:0] rom_data;
+logic rom_enable;
+// Keep track of pipeline delay so we don't write garbage into the buffer
+logic delay;
+
+// Keep track of if we are caught up to the buffer or not
+logic waiting;
+//TODO: This probably could be an assign, not sure
+
+assign ready = '1;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        delay <= 1;
+        rom_address <= 0;
+        initializing <= 1;
+        audio_buffer.addra <= 0;
+        audio_buffer.ena <= 0;
+    end
+    else if (initializing) begin
+        rom_enable <= 1;
+        case (delay)
+            1:  delay <= 0;
+            0:  begin
+                rom_address <= 1;
+                delay <= 0;
+                initializing <= 0;
+                end
+        endcase
+    end
+    else begin
+        if (!waiting) begin
+            audio_buffer.ena <= 1;
+            audio_buffer.dina <= rom_data;
+            audio_buffer.addra <= audio_buffer.addra + 1;
+        end
+
+    end
+
+    
+
+end
+
+
+// xpm_memory_sprom: Single Port ROM
+// Xilinx Parameterized Macro, version 2024.2
+
+// The ROM has 17 address bits and 8 data bits to store 128KiB, more than
+// enough for one second of 48khz audio
+xpm_memory_sprom #(
+  .ADDR_WIDTH_A(17),              // DECIMAL
+  .AUTO_SLEEP_TIME(0),           // DECIMAL
+  .CASCADE_HEIGHT(0),            // DECIMAL
+  .ECC_BIT_RANGE("7:0"),         // String
+  .ECC_MODE("no_ecc"),           // String
+  .ECC_TYPE("none"),             // String
+  .IGNORE_INIT_SYNTH(0),         // DECIMAL
+  .MEMORY_INIT_FILE("roundabout.mem"),     // String
+  .MEMORY_INIT_PARAM("0"),       // String
+  .MEMORY_OPTIMIZATION("true"),  // String
+  .MEMORY_PRIMITIVE("auto"),     // String
+  .MEMORY_SIZE(131072*8),            // DECIMAL
+  .MESSAGE_CONTROL(0),           // DECIMAL
+  .RAM_DECOMP("auto"),           // String
+  .READ_DATA_WIDTH_A(8),        // DECIMAL
+  .READ_LATENCY_A(2),            // DECIMAL
+  .READ_RESET_VALUE_A("0"),      // String
+  .RST_MODE_A("SYNC"),           // String
+  .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .USE_MEM_INIT(1),              // DECIMAL
+  .USE_MEM_INIT_MMI(0),          // DECIMAL
+  .WAKEUP_TIME("disable_sleep")  // String
+)
+xpm_memory_sprom_inst (
+  .douta(rom_data),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+  .addra(rom_address),                   // ADDR_WIDTH_A-bit input: Address for port A read operations.
+  .clka(clk),                     // 1-bit input: Clock signal for port A.
+  .ena(rom_enable),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
+                                   // cycles when read operations are initiated. Pipelined internally.
+
+  .rsta(reset)                     // 1-bit input: Reset signal for the final port A output register stage.
+                                   // Synchronously resets output port douta to the value specified by
+                                   // parameter READ_RESET_VALUE_A.
+);
+
+// End of xpm_memory_sprom_inst instantiation
+				
+
+endmodule

design/seconds_display.sv

@@ -1,10 +0,0 @@
-module seconds_display(
-    input logic clk, 
-    input logic reset, 
-    input [$clog2(60)-1:0] counter,
-    output [7:0] display_tens,
-    output [7:0] display_ones
-);
-
-
-endmodule

design/segment_display/display_anode_driver.sv

@@ -0,0 +1,20 @@
+// NOTE: This expects to be driven with a 100khz clock
+module display_anode_driver(
+    input logic clk, 
+    input logic reset, 
+    output logic [7:0] AN, 
+    output logic [2:0] mux_select);
+
+// This is just a shift register that drives each anode individually
+always_ff @(posedge clk) begin
+    if (reset) begin
+        AN <= '1 - 1;
+        mux_select <= 0;
+    end
+    else begin
+        AN <= {AN[6:0], AN[7]};
+        // Letting this overflow will automatically reset it
+        mux_select <= mux_select + 1;
+    end
+end
+endmodule

design/segment_display/display_converter.sv

@@ -0,0 +1,60 @@
+/**
+* display_converter.sv - decodes a 5 bit digit input into its seven segment
+*                        display equivalent using a lookup table. Display can
+*                        do 0 - 9, A - F, individual segmentsm and special
+*                        characters.  
+* @author: Dilanthi Prentice, Waylon Cude
+* @date: 6/12/25
+*
+*
+****/
+module display_converter(
+    input logic [4:0] digit, 
+    output logic [6:0] segment
+);
+
+localparam ROM_SIZE=32;
+
+//ROM lookup table for seven segment display
+localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
+    7'b1111110, //0
+    7'b0000110, //1
+    7'b1101101, //2
+    7'b1111001, //3
+    7'b0110011, //4
+    7'b1011011, //5
+    7'b1011111, //6
+    7'b1110000, //7
+    7'b1111111, //8
+    7'b1111011, //9
+
+    7'b1110111, //A
+    7'b0011111, //B
+    7'b1001110, //C
+    7'b0111101, //D
+    7'b1001111, //E
+    7'b1000111, //F
+
+    7'b1000000, //segment a
+    7'b0100000, //segment b
+    7'b0010000, //segment c
+    7'b0001000, //segment d
+    7'b0000100, //segment e
+    7'b0000001, //segment f
+
+    7'b0110111, //H
+    7'b0001110, //L
+    7'b1110111, //R
+    7'b0000110, //l 
+    7'b0000101, //r
+
+    7'b0000000, //blank
+    7'b0000000, //blank
+    7'b0000000, //blank
+    7'b0000000, //blank
+    7'b0000000  //blank
+};
+//use digit input to index segment_rom lookup table.
+assign segment = segment_rom[digit];
+
+endmodule

design/segment_display/seconds_display.sv

@@ -0,0 +1,29 @@
+/***
+* seconds_display.sv - convert a seconds counter to a seven segement display.
+*
+* @author: Dilanthi Prentice, Waylon Cude
+* @date: 6/12/25
+*
+*/
+module seconds_display
+(
+    input [$clog2(60)-1:0] seconds,
+    output [6:0] display_tens,      
+    output [6:0] display_ones       
+);
+
+logic [4:0] ones_digit; 
+logic [4:0] tens_digit;
+
+always_comb
+begin
+    ones_digit = seconds % 10;
+    tens_digit = seconds / 10;
+end
+
+//instantiate the display_converter to convert the counter
+//to a seven segment display number
+display_converter ones (ones_digit, display_ones);
+display_converter tens (tens_digit, display_tens);
+
+endmodule

doc/bugs.md

@@ -0,0 +1,14 @@
+## Bugs I Found
+
+### Audio Buffer
+- Forgot to assign to a delay counter
+
+### Debouncer
+- Logic was fundamentally wrong
+- Found multiple logic bugs with testbench and then assertions
+
+### Display Converter
+- Found a typo in a single digit
+
+### Low Freq Clock Gen
+- Was initially trying to do modulo at max clock speed, failing timing

doc/rom_sd.gv

@@ -0,0 +1,23 @@
+digraph rom_sd {
+    Reset [shape = doublecircle, label = "RESET\nbuffer_half = 0\nrom_address = 0\nrom_enable = 1\nbuf.addr=0\nready=0"];
+    node [shape = circle];
+    Delay [label="DELAY\nrom_address++"];
+    WriteBuf [label="WRITEBUF\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nrom_addr++"];
+    EndWrite [label="ENDWRITE\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nready=1"];
+    Wait [label = "WAIT\nbuf.ena=0"];
+
+    Reset -> Reset [label="reset"];
+    Reset -> Delay [label="!reset"];
+
+    Delay -> WriteBuf;
+
+    WriteBuf -> WriteBuf [label="buf.addr < 1023"]
+    WriteBuf -> EndWrite [label="buf.addr == 1023"]
+
+    EndWrite -> Wait;
+
+    Wait -> Wait [label = "buffer_half == buf.address_half"]
+    Wait -> Delay [label = "buffer_half != buf.address_half"]
+
+
+}

lib/assertion_error.sv

@@ -0,0 +1,5 @@
+// A global error counter, useful for when we're tracking error counts from
+// assertions
+package assertion_error;
+   int errors;
+endpackage : assertion_error

lib/audio_buffer_interface.sv

@@ -0,0 +1,18 @@
+interface audio_buffer_interface;
+    logic [10:0] addra;
+    logic [7:0] dina;
+    logic clka;
+    logic ena;
+    logic address_half;
+
+    modport driver (
+        output addra, dina, clka, ena,
+        input address_half
+    );
+
+    modport receiver (
+        input addra, dina, clka, ena,
+        output address_half
+    );
+
+endinterface

lib/sdvd_defs.sv

@@ -0,0 +1,7 @@
+`ifndef SDVD_DEFS
+`define SDVD_DEFS
+package sdvd_defs;
+    // Playback speed type
+    typedef logic [3:0] SPEED;
+endpackage
+`endif

verification/audio/audio_buffer_tb.sv

@@ -0,0 +1,124 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+
+module audio_buffer_tb;
+    logic clk, reset;
+
+    // Control signals
+    logic play, stop;
+    SPEED speed;
+
+    // Whether the current address being read from is in the upper or lower
+    // half of the 2KiB buffer
+    logic address_half;
+
+    // Whether the audio buffer is currently playing
+    logic playing;
+
+    // A 16-bit audio sample to output
+    logic [15:0] sample;
+
+    // Inputs for the memory buffer
+    logic [10:0] addra;
+    logic [7:0] dina;
+    logic clka, ena;
+
+    logic [9:0] counter;
+
+    logic [15:0] test_memory [1023:0];
+    audio_buffer dut(.*);
+
+    // The writer's clock should be much faster than the 48khz buffer clock
+    initial clka = 0;
+    always #5 clka = ~clka;
+
+
+    // An order of magnitude difference is fine
+    initial clk = 0;
+    always #50 clk = ~clk;
+
+    // Reader
+    initial begin
+        `ifdef DEBUG
+        $monitor("PLAYING: %b ADDR: 0x%x DATA: 0x%x WILLDELAY: %b",
+                 playing, dut.address, dut.doutb,dut.delay);
+        `endif
+        fork
+        //Reader
+        begin
+            play = 0;
+            stop = 0;
+            clk = 0;
+            reset = 0;
+            speed = 1;
+            @(posedge clk)
+            reset = 1;
+            @(posedge clk)
+            reset = 0;
+            play = 1;
+            @(posedge clk)
+            assert (playing == 1) else $error("Audio buffer not playing");
+            // Wait an extra clock cycle because of the blockmem delay
+            @(posedge clk)
+            // The most basic test we can do here is an incrementing counter,
+            // where the stored sample is the same as the address
+            $display("Running linear test");
+            for (counter = 0; counter != 1023; counter++) begin
+                #1
+                assert ({6'b0, counter} === sample) else
+                    $error("Invalid sample, expected 0x%x but found 0x%x",counter,sample);
+                @(posedge clk);
+            end
+            @(posedge clk);
+            $display("Running randomized test");
+            for (counter = 0; counter != 1023; counter++) begin
+                #1
+                assert (test_memory[counter] === sample) else
+                    $error("Invalid sample, expected 0x%x but found 0x%x",test_memory[counter],sample);
+                @(posedge clk);
+            end
+
+        end
+        // Writer
+        begin
+            ena = 1;
+            for (int i = 0; i<= 1024; i++) begin
+                addra = i*2;
+                dina = i[7:0];
+                @(posedge clka)
+                addra = i*2+1;
+                dina = i[15:8];
+                @(posedge clka);
+            end
+            wait (address_half==1);
+            // random test, write to lower half of memory
+            for (int i = 0; i< 512; i++) begin
+                addra = i*2;
+                dina = $urandom;
+                test_memory[i][7:0] = dina;
+                @(posedge clka)
+                addra = i*2+1;
+                dina = $urandom;
+                test_memory[i][15:8] = dina;
+                @(posedge clka);
+            end
+            wait (address_half==0);
+            // random test, write to upper half of memory
+            for (int i = 512; i< 1024; i++) begin
+                addra = i*2;
+                dina = $urandom;
+                test_memory[i][7:0] = dina;
+                @(posedge clka)
+                addra = i*2+1;
+                dina = $urandom;
+                test_memory[i][15:8] = dina;
+                @(posedge clka);
+            end
+        end
+        join
+        $finish;
+    end
+
+endmodule

verification/audio/pwn_tb.sv

@@ -0,0 +1,6 @@
+/*****
+ * pwn_tb.sv - testbench for the pwn.sv module. 
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/2025
+ * */

verification/debouncer_assertions.sv

@@ -0,0 +1,34 @@
+`ifdef VERILATOR
+    `include "assertion_error.sv"
+`endif
+module debouncer_assertions(input logic clk, reset,source, out);
+
+// Check that no matter how long the button is held down, output will only be
+// high once
+property only_one_per_press_p;
+    (source && out) |=> (source |-> ((!out) throughout (source[+])));
+endproperty
+only_one_per_press_a: assert property (@(posedge clk) only_one_per_press_p) 
+    else assertion_error::errors++;
+
+// Check that the output is never high two cycles in a row
+property out_not_high_consecutively_p;
+    out |=> !out;
+endproperty
+out_not_high_consecutively_a: assert property (@(posedge clk) out_not_high_consecutively_p)
+    else assertion_error::errors++;
+
+// Check that the output always turns off if the button is depressed
+property off_if_depressed_p;
+    !source |-> !out;
+endproperty
+off_if_depressed_a: assert property (@(posedge clk) off_if_depressed_p)
+    else assertion_error::errors++;
+
+// Check that the output activates if the button is pressed
+property on_if_pressed_p;
+    !source |=> (source |-> out);
+endproperty
+on_if_pressed_a: assert property (@(posedge clk) on_if_pressed_p);
+
+endmodule

verification/debouncer_tb.sv

@@ -1,8 +1,77 @@
+`timescale 1ns / 1ps
+
+`ifdef VERILATOR
+    `include "assertion_error.sv"
+`endif
+import assertion_error::errors;
 module debouncer_tb;
 
+parameter TESTCYCLES=1000;
+
 logic clk,reset,source;
 wire out;
 
 debouncer Dut (.*);
+bind debouncer debouncer_assertions AssertDut (.*);
 
+initial begin
+    clk = 0;
+    forever #10 clk = ~clk;
+end
+
+initial begin
+    // Turn assertions off during reset
+    $assertoff;
+    $display("Testing debouncer");
+    reset = 1;
+    source = 0;
+    @(posedge clk);
+    @(posedge clk);
+    reset = 0;
+    $asserton;
+    @(posedge clk);
+    source = 1;
+    #1;
+    assert (out == 1) else begin
+        $error("Output not brought high during first press");
+        errors++;
+    end
+    @(posedge clk);
+    #1;
+    assert (out == 0) else begin
+        $error("Output not brought low after first press");
+        errors++;
+    end
+    @(posedge clk);
+    source = 0;
+    @(posedge clk);
+    source = 1;
+    #1;
+    assert (out == 1) else begin
+        $error("Output not brought high during second press");
+        errors++;
+    end
+    @(posedge clk);
+    source = 0;
+    @(posedge clk);
+    #1;
+    assert (out == 0) else begin
+        $error("Output not brought low after second press");
+        errors++;
+    end
+
+    $display("Generating random input to test assertions");
+    for (int i=0; i<TESTCYCLES; i++) begin
+        source = $urandom;
+        @(posedge clk);
+    end
+
+    if (errors == 0)
+        $display("Found no errors while testing debouncer");
+    else
+        $display("ERROR: Found %0d errors while testing debouncer", errors);
+
+    $finish;
+
+end
 endmodule

verification/playback_controller_tb.sv

@@ -0,0 +1,108 @@
+/****
+* playback_controller_tb.sv - a testbench for the playback_controller.sv
+*                             module.
+*                             
+* @author: Dilanthi Prentice
+* @date: [unsure of due date]
+*
+* */
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+
+module playback_controller_tb; 
+    logic clk, reset;
+    logic play, ff;
+    SPEED speed;
+    int errors;
+
+    //instatiate the dut
+    playback_controller dut(clk, reset, play, ff, speed);
+
+    //clock generation
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    //play button press
+    task press_play();
+        play = 1;
+        @(posedge clk);
+        play = 0;
+        @(posedge clk);
+    endtask
+
+    //ff button press
+    task press_ff();
+        ff = 1;
+        @(posedge clk);
+        ff = 0;
+        @(posedge clk);
+    endtask
+
+    initial
+    begin
+        @(posedge clk);
+        play = 0;
+        ff = 0;
+        
+        reset = 1;
+        @(posedge clk);
+        reset = 0;
+        
+        @(posedge clk);
+        assert (speed === 0) else
+            begin    
+            $error("Speed not zero after reset");
+            errors++;
+            end
+       @(posedge clk);
+        
+        press_play();
+        assert (speed === 1) else
+            begin
+            $error("Play not working");
+            errors++;
+            end
+
+        press_play();
+        assert (speed === 0) else
+            begin
+            $error("Pause not working");
+            errors++;
+            end
+
+        press_ff();
+        assert (speed === 2) else
+            begin
+            $error("Not in FF2 after ff btn pressed once");
+            errors++;
+            end
+
+        press_ff();
+        assert (speed === 4) else
+            begin
+            $error("Not in FF4 after ff btn pressed twice");
+            errors++;
+            end
+        
+        press_ff();
+        assert (speed === 8) else
+            begin
+            $error("Not in FF8 after ff btn pressed thrice");
+            errors++;
+            end
+
+        press_play();
+        assert (speed === 0) else
+            begin
+            $error("Unsuccessful return to pause after play btn pressed from a FF state");
+            errors++;
+            end
+
+        if (errors === 0)
+            $display("No errors detected in playback_controller");
+        
+        $finish;
+    end
+endmodule

verification/segment_display/seconds_display_tb.sv

@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 module seconds_display_tb;
 int errors = 0;
 logic [5:0] seconds;
@@ -16,14 +17,16 @@ initial begin
         #1
         if (display_ones !== expected_ones) begin
             errors++;
-            $display("Failed ones test case, displayed = %b, expected = %b",
+            $error("Failed ones test case, seconds = %d, displayed = %b, expected = %b",
+                     seconds,
                      display_ones,
                      expected_ones);
         end
         else
         if (display_tens !== expected_tens) begin
             errors++;
-            $display("Failed tens test case, displayed = %b, expected = %b",
+            $error("Failed tens test case, seconds = %d, displayed = %b, expected = %b",
+                     seconds,
                      display_tens,
                      expected_tens);
         end