uelen 2fde75a330 Added a in-progress top file ...

Some of this stuff should get split out into 7-segment logic probably,
having logic in the top file seems like a bad call

2025-05-19 15:21:53 -07:00

.woodpecker

Add a wowrkflow to test that everything works

2025-05-07 17:40:55 -07:00

design

Added a in-progress top file

2025-05-19 15:21:53 -07:00

verification

Add testbench for the seconds display

2025-05-17 12:40:20 -07:00

.gitignore

Add vivado project

2025-05-16 17:16:08 -07:00

modules.md

Initial commit

2025-05-06 13:46:53 -07:00

Nexys-A7-100T-Master.xdc

Added a in-progress top file

2025-05-19 15:21:53 -07:00

SDVD.xpr

Added a in-progress top file

2025-05-19 15:21:53 -07:00

S

Description

An FPGA video player

353 MiB

Languages

SystemVerilog 73.3%

Tcl 26.6%

Python 0.1%