Added a in-progress top file
Some of this stuff should get split out into 7-segment logic probably, having logic in the top file seems like a bad call
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da7d026d06
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@ -5,8 +5,8 @@
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## Note: As the Nexys 4 DDR was rebranded to the Nexys A7 with no substantial changes, this XDC file will also work for the Nexys 4 DDR.
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## Clock signal
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#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
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set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
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##Switches
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@ -54,31 +54,31 @@
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
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##7 segment display
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#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
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#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
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#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
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#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
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#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
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set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
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set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
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set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
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set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
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set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
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set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
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set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
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#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
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#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
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#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
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#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
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#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
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set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
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set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
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set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
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set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
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set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
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set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
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set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
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##CPU Reset Button
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#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
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set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
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##Buttons
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
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set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
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#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
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#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
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#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
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set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
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20
SDVD.xpr
20
SDVD.xpr
@ -48,6 +48,7 @@
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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@ -98,6 +99,13 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/display_anode_driver.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/playback_controller.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -107,7 +115,13 @@
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</File>
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<File Path="$PPRDIR/design/seconds_display.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/nexys_a7_top.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@ -115,7 +129,7 @@
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="Playback_Controller"/>
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<Option Name="TopModule" Val="nexys_a7_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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@ -143,7 +157,7 @@
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="Playback_Controller"/>
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<Option Name="TopModule" Val="nexys_a7_top"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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11
design/display_anode_driver.sv
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11
design/display_anode_driver.sv
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@ -0,0 +1,11 @@
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// NOTE: This expects to be driven with a 100khz clock
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module display_anode_driver(input logic clk, input logic reset, output logic [7:0] AN);
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// This is just a shift register that drives each anode individually
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always_ff @(posedge clk) begin
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if (reset)
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AN <= 1;
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else
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AN <= {AN[6:0], AN[7]};
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end
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endmodule
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45
design/low_freq_clock_gen.sv
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45
design/low_freq_clock_gen.sv
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@ -0,0 +1,45 @@
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`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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// Takes in a 100MHz clock and generates the very low freq signals needed
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// for driving the control logic
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module low_freq_clock_gen(
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input logic clk, reset,
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input SPEED speed,
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output logic clk1k, clk10h, seconds_pulse
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);
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logic [$clog2(100_000_000):0] counter;
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logic [$clog2(4000):0] seconds_counter;
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logic clk4k;
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assign clk1k = (counter % (100_000_000/1000)) != 0;
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assign clk10h = (counter % (100_000_000/10)) != 0;
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assign clk4k = (counter % (100_000_000/4000)) != 0;
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always_ff @(posedge clk) begin
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// NOTE: This generates a pulse on the same clock cycle that reset is
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// asserted. Is that bad??
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if (reset)
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counter <= 0;
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// Roll the counter over back to zero every second
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else if (counter == 99_999_999)
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counter <= 0;
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else
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counter <= counter + 1;
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// This logic handles the variable-speed seconds counter
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if (reset) begin
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seconds_pulse <= 0;
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seconds_counter <= 0;
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end
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else if (clk4k && seconds_counter >= 4000) begin
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seconds_counter <= seconds_counter-4000;
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seconds_pulse <= 1;
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end
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else if (clk4k) begin
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seconds_pulse <= 0;
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seconds_counter <= seconds_counter + {9'b0, speed};
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end
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end
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endmodule
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67
design/nexys_a7_top.sv
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67
design/nexys_a7_top.sv
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@ -0,0 +1,67 @@
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`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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module nexys_a7_top(
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input logic CLK100MHZ, CPU_RESETN,
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input logic BTNC, BTNR,
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output logic [7:0] CA,CB,CC,CD,CE,CF,CG,
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output logic [7:0] AN
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);
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// Active high reset
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wire reset;
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assign reset = ~CPU_RESETN;
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logic clk_1khz, clk_10hz;
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logic seconds_pulse;
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SPEED speed;
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// Map C{A-G} to an array of 7-segment displays
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wire [6:0] segments [7:0];
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for (genvar i = 0; i<8; i++) begin: segmentGenerate
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assign {CG[i],CF[i],CE[i],CD[i],CC[i],CB[i],CA[i]} = segments[i];
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end
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logic [$clog2(60):0] seconds;
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logic [$clog2(60):0] minutes;
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logic [$clog2(60):0] hours;
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low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
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// Count the number on seconds, hours, and minutes elapsed
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// If the speed is faster this will pulse more often than once a second
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// but will still theoretically be a second of video time
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always_ff @(posedge seconds_pulse) begin
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if (reset) begin
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seconds <= 0;
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minutes <= 0;
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hours <= 0;
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end
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else if (seconds == 59) begin
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seconds <= 0;
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if (minutes == 59) begin
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minutes <= 0;
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hours <= hours + 1;
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end
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else
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minutes <= minutes + 1;
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end
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else
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seconds <= seconds + 1;
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end
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display_anode_driver anodeDriver(clk_1khz,reset,AN);
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seconds_display secondsSegment (seconds, segments[1], segments[0]);
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seconds_display minutesSegment (minutes, segments[3], segments[2]);
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seconds_display hoursSegment (hours, segments[5], segments[4]);
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// Run the playback speed state machine at a lower rate
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// Gets rid of button bouncing
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playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
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endmodule
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@ -1,4 +1,7 @@
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module Playback_Controller(
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`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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module playback_controller(
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// This clock should be reasonably slow
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input logic clk,
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input logic reset,
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@ -8,7 +11,7 @@ module Playback_Controller(
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input logic ff,
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// Output is 0, 1x, 2x, 4x, or 8x
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output wire [3:0] speed
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output SPEED speed
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);
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wire play_pulse,ff_pulse;
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7
design/sdvd_defs.sv
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7
design/sdvd_defs.sv
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@ -0,0 +1,7 @@
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`ifndef SDVD_DEFS
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`define SDVD_DEFS
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package sdvd_defs;
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// Playback speed type
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typedef logic [3:0] SPEED;
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endpackage
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`endif
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