uelen/SDVD
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Dilanthi 4b041651d4
ci/woodpecker/push/test-workflow Pipeline was successful
Details
added seven segment display logic / seconds counter
2025-05-17 20:38:52 -07:00
.woodpecker
Add a wowrkflow to test that everything works
2025-05-07 17:40:55 -07:00
design
added seven segment display logic / seconds counter
2025-05-17 20:38:52 -07:00
verification
Add empty debouncer tb
2025-05-16 18:53:05 -07:00
.gitignore
Add vivado project
2025-05-16 17:16:08 -07:00
modules.md
Initial commit
2025-05-06 13:46:53 -07:00
Nexys-A7-100T-Master.xdc
Add vivado project
2025-05-16 17:16:08 -07:00
SDVD.xpr
Commit the project file again
2025-05-16 19:27:02 -07:00
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Description
An FPGA video player
353 MiB
Languages
SystemVerilog 73.3%
Tcl 26.6%
Python 0.1%