All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
added x16 fast forward speed to playback_controller.sv corrected dates on pwn.sv, playback_controller.sv, display_converter.sv, and seconds_display.sv
Description
An FPGA video player
Languages
SystemVerilog
73.3%
Tcl
26.6%
Python
0.1%