comment clean up

comment clean up for segment_display folder
code clean up for playback_controller.sv
2025-06-10 02:51:18 -07:00 · 2025-06-10 01:38:52 -07:00 · 2025-06-10 01:30:51 -07:00 · 2025-06-09 15:41:13 -07:00 · 2025-06-07 21:57:17 -07:00 · 2025-06-06 20:49:18 -07:00
52 changed files with 869705 additions and 135 deletions
@@ -2,4 +2,6 @@
 *.log
 xsim.dir
 SDVD.*
+.Xil/
+vivado_pid*
 !SDVD.xpr
@@ -31,7 +31,7 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
 #set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]

 ## LEDs
-#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {LED[0]}]
 #set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
 #set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
 #set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
@@ -153,14 +153,14 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports BTNR]
 #set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs

 ##Micro SD Connector
-#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
-#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
-#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
-#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
-#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
-#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
-#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
-#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
+set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports SD_RESET]
+set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports SD_CD]
+set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports SD_SCK]
+set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports SD_CMD]
+set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[0]}]
+set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[1]}]
+set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[2]}]
+set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[3]}]

 ##Accelerometer
 #set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
@@ -182,8 +182,8 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports BTNR]
 #set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel

 ##PWM Audio Amplifier
-#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
-#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports AUD_PWM]
+set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports AUD_SD]

 ##USB-RS232 Interface
 #set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
@@ -216,12 +216,36 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports BTNR]
 #set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
 #set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn

+
+connect_debug_port u_ila_0/probe2 [get_nets [list {realSdPlayer/address[0]} {realSdPlayer/address[1]} {realSdPlayer/address[2]} {realSdPlayer/address[3]} {realSdPlayer/address[4]} {realSdPlayer/address[5]} {realSdPlayer/address[6]} {realSdPlayer/address[7]} {realSdPlayer/address[8]} {realSdPlayer/address[9]} {realSdPlayer/address[10]} {realSdPlayer/address[11]} {realSdPlayer/address[12]} {realSdPlayer/address[13]} {realSdPlayer/address[14]} {realSdPlayer/address[15]} {realSdPlayer/address[16]} {realSdPlayer/address[17]} {realSdPlayer/address[18]} {realSdPlayer/address[19]} {realSdPlayer/address[20]} {realSdPlayer/address[21]} {realSdPlayer/address[22]} {realSdPlayer/address[23]} {realSdPlayer/address[24]} {realSdPlayer/address[25]} {realSdPlayer/address[26]} {realSdPlayer/address[27]} {realSdPlayer/address[28]} {realSdPlayer/address[29]} {realSdPlayer/address[30]} {realSdPlayer/address[31]}]]
+
+
+set_property MARK_DEBUG true [get_nets reset]
+
+
+
+
+
+
+
+connect_debug_port u_ila_0/probe4 [get_nets [list {realSdPlayer/reader/next_state[0]} {realSdPlayer/reader/next_state[1]} {realSdPlayer/reader/next_state[2]}]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {realSdPlayer/reader/state[0]} {realSdPlayer/reader/state[1]} {realSdPlayer/reader/state[2]}]]
+
+connect_debug_port u_ila_0/probe6 [get_nets [list {realSdPlayer/sender/to_send[0]} {realSdPlayer/sender/to_send[1]} {realSdPlayer/sender/to_send[2]} {realSdPlayer/sender/to_send[3]} {realSdPlayer/sender/to_send[4]} {realSdPlayer/sender/to_send[5]} {realSdPlayer/sender/to_send[6]} {realSdPlayer/sender/to_send[7]} {realSdPlayer/sender/to_send[8]} {realSdPlayer/sender/to_send[9]} {realSdPlayer/sender/to_send[10]} {realSdPlayer/sender/to_send[11]} {realSdPlayer/sender/to_send[12]} {realSdPlayer/sender/to_send[13]} {realSdPlayer/sender/to_send[14]} {realSdPlayer/sender/to_send[15]} {realSdPlayer/sender/to_send[16]} {realSdPlayer/sender/to_send[17]} {realSdPlayer/sender/to_send[18]} {realSdPlayer/sender/to_send[19]} {realSdPlayer/sender/to_send[20]} {realSdPlayer/sender/to_send[21]} {realSdPlayer/sender/to_send[22]} {realSdPlayer/sender/to_send[23]} {realSdPlayer/sender/to_send[24]} {realSdPlayer/sender/to_send[25]} {realSdPlayer/sender/to_send[26]} {realSdPlayer/sender/to_send[27]} {realSdPlayer/sender/to_send[28]} {realSdPlayer/sender/to_send[29]} {realSdPlayer/sender/to_send[30]} {realSdPlayer/sender/to_send[31]} {realSdPlayer/sender/to_send[32]} {realSdPlayer/sender/to_send[33]} {realSdPlayer/sender/to_send[34]} {realSdPlayer/sender/to_send[35]} {realSdPlayer/sender/to_send[36]} {realSdPlayer/sender/to_send[37]} {realSdPlayer/sender/to_send[38]} {realSdPlayer/sender/to_send[39]} {realSdPlayer/sender/to_send[40]} {realSdPlayer/sender/to_send[41]} {realSdPlayer/sender/to_send[42]} {realSdPlayer/sender/to_send[43]} {realSdPlayer/sender/to_send[44]} {realSdPlayer/sender/to_send[45]} {realSdPlayer/sender/to_send[46]} {realSdPlayer/sender/to_send[47]}]]
+
+set_property MARK_DEBUG true [get_nets realSdPlayer/fast_clk]
+connect_debug_port u_ila_0/probe8 [get_nets [list {realSdPlayer/fastSender/to_send[0]} {realSdPlayer/fastSender/to_send[1]} {realSdPlayer/fastSender/to_send[2]} {realSdPlayer/fastSender/to_send[3]} {realSdPlayer/fastSender/to_send[4]} {realSdPlayer/fastSender/to_send[5]} {realSdPlayer/fastSender/to_send[6]} {realSdPlayer/fastSender/to_send[7]} {realSdPlayer/fastSender/to_send[8]} {realSdPlayer/fastSender/to_send[9]} {realSdPlayer/fastSender/to_send[10]} {realSdPlayer/fastSender/to_send[11]} {realSdPlayer/fastSender/to_send[12]} {realSdPlayer/fastSender/to_send[13]} {realSdPlayer/fastSender/to_send[14]} {realSdPlayer/fastSender/to_send[15]} {realSdPlayer/fastSender/to_send[16]} {realSdPlayer/fastSender/to_send[17]} {realSdPlayer/fastSender/to_send[18]} {realSdPlayer/fastSender/to_send[19]} {realSdPlayer/fastSender/to_send[20]} {realSdPlayer/fastSender/to_send[21]} {realSdPlayer/fastSender/to_send[22]} {realSdPlayer/fastSender/to_send[23]} {realSdPlayer/fastSender/to_send[24]} {realSdPlayer/fastSender/to_send[25]} {realSdPlayer/fastSender/to_send[26]} {realSdPlayer/fastSender/to_send[27]} {realSdPlayer/fastSender/to_send[28]} {realSdPlayer/fastSender/to_send[29]} {realSdPlayer/fastSender/to_send[30]} {realSdPlayer/fastSender/to_send[31]} {realSdPlayer/fastSender/to_send[32]} {realSdPlayer/fastSender/to_send[33]} {realSdPlayer/fastSender/to_send[34]} {realSdPlayer/fastSender/to_send[35]} {realSdPlayer/fastSender/to_send[36]} {realSdPlayer/fastSender/to_send[37]} {realSdPlayer/fastSender/to_send[38]} {realSdPlayer/fastSender/to_send[39]} {realSdPlayer/fastSender/to_send[40]} {realSdPlayer/fastSender/to_send[41]} {realSdPlayer/fastSender/to_send[42]} {realSdPlayer/fastSender/to_send[43]} {realSdPlayer/fastSender/to_send[44]} {realSdPlayer/fastSender/to_send[45]} {realSdPlayer/fastSender/to_send[46]} {realSdPlayer/fastSender/to_send[47]}]]
+connect_debug_port u_ila_0/probe19 [get_nets [list realSdPlayer/send_command_ready_fast]]
+connect_debug_port u_ila_0/probe21 [get_nets [list realSdPlayer/send_command_start_fast]]
+
+
+set_property MARK_DEBUG true [get_nets realSdPlayer/sd_cmd_OBUF]
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0]
 set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
 set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
 set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
@@ -229,55 +253,91 @@ set_property port_width 1 [get_debug_ports u_ila_0/clk]
 connect_debug_port u_ila_0/clk [get_nets [list CLK100MHZ_IBUF_BUFG]]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
 set_property port_width 6 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {seconds_reg[0]} {seconds_reg[1]} {seconds_reg[2]} {seconds_reg[3]} {seconds_reg[4]} {seconds_reg[5]}]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {realSdPlayer/next_state[0]} {realSdPlayer/next_state[1]} {realSdPlayer/next_state[2]} {realSdPlayer/next_state[3]} {realSdPlayer/next_state[4]} {realSdPlayer/next_state[5]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
 set_property port_width 6 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {minutes[0]} {minutes[1]} {minutes[2]} {minutes[3]} {minutes[4]} {minutes[5]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {realSdPlayer/state[0]} {realSdPlayer/state[1]} {realSdPlayer/state[2]} {realSdPlayer/state[3]} {realSdPlayer/state[4]} {realSdPlayer/state[5]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 3 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {playbackController/current[0]} {playbackController/current[1]} {playbackController/current[2]}]]
+set_property port_width 11 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {realSdPlayer/dataHandler/buffer\\.addra[0]} {realSdPlayer/dataHandler/buffer\\.addra[1]} {realSdPlayer/dataHandler/buffer\\.addra[2]} {realSdPlayer/dataHandler/buffer\\.addra[3]} {realSdPlayer/dataHandler/buffer\\.addra[4]} {realSdPlayer/dataHandler/buffer\\.addra[5]} {realSdPlayer/dataHandler/buffer\\.addra[6]} {realSdPlayer/dataHandler/buffer\\.addra[7]} {realSdPlayer/dataHandler/buffer\\.addra[8]} {realSdPlayer/dataHandler/buffer\\.addra[9]} {realSdPlayer/dataHandler/buffer\\.addra[10]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 6 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {hours_reg[0]} {hours_reg[1]} {hours_reg[2]} {hours_reg[3]} {hours_reg[4]} {hours_reg[5]}]]
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {realSdPlayer/arg[0]} {realSdPlayer/arg[1]} {realSdPlayer/arg[2]} {realSdPlayer/arg[3]} {realSdPlayer/arg[4]} {realSdPlayer/arg[5]} {realSdPlayer/arg[6]} {realSdPlayer/arg[7]} {realSdPlayer/arg[8]} {realSdPlayer/arg[9]} {realSdPlayer/arg[10]} {realSdPlayer/arg[11]} {realSdPlayer/arg[12]} {realSdPlayer/arg[13]} {realSdPlayer/arg[14]} {realSdPlayer/arg[15]} {realSdPlayer/arg[16]} {realSdPlayer/arg[17]} {realSdPlayer/arg[18]} {realSdPlayer/arg[19]} {realSdPlayer/arg[20]} {realSdPlayer/arg[21]} {realSdPlayer/arg[22]} {realSdPlayer/arg[23]} {realSdPlayer/arg[24]} {realSdPlayer/arg[25]} {realSdPlayer/arg[26]} {realSdPlayer/arg[27]} {realSdPlayer/arg[28]} {realSdPlayer/arg[29]} {realSdPlayer/arg[30]} {realSdPlayer/arg[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 3 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {anodeDriver/mux_select[0]} {anodeDriver/mux_select[1]} {anodeDriver/mux_select[2]}]]
+set_property port_width 48 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {realSdPlayer/received_data[0]} {realSdPlayer/received_data[1]} {realSdPlayer/received_data[2]} {realSdPlayer/received_data[3]} {realSdPlayer/received_data[4]} {realSdPlayer/received_data[5]} {realSdPlayer/received_data[6]} {realSdPlayer/received_data[7]} {realSdPlayer/received_data[8]} {realSdPlayer/received_data[9]} {realSdPlayer/received_data[10]} {realSdPlayer/received_data[11]} {realSdPlayer/received_data[12]} {realSdPlayer/received_data[13]} {realSdPlayer/received_data[14]} {realSdPlayer/received_data[15]} {realSdPlayer/received_data[16]} {realSdPlayer/received_data[17]} {realSdPlayer/received_data[18]} {realSdPlayer/received_data[19]} {realSdPlayer/received_data[20]} {realSdPlayer/received_data[21]} {realSdPlayer/received_data[22]} {realSdPlayer/received_data[23]} {realSdPlayer/received_data[24]} {realSdPlayer/received_data[25]} {realSdPlayer/received_data[26]} {realSdPlayer/received_data[27]} {realSdPlayer/received_data[28]} {realSdPlayer/received_data[29]} {realSdPlayer/received_data[30]} {realSdPlayer/received_data[31]} {realSdPlayer/received_data[32]} {realSdPlayer/received_data[33]} {realSdPlayer/received_data[34]} {realSdPlayer/received_data[35]} {realSdPlayer/received_data[36]} {realSdPlayer/received_data[37]} {realSdPlayer/received_data[38]} {realSdPlayer/received_data[39]} {realSdPlayer/received_data[40]} {realSdPlayer/received_data[41]} {realSdPlayer/received_data[42]} {realSdPlayer/received_data[43]} {realSdPlayer/received_data[44]} {realSdPlayer/received_data[45]} {realSdPlayer/received_data[46]} {realSdPlayer/received_data[47]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 8 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {AN_OBUF[0]} {AN_OBUF[1]} {AN_OBUF[2]} {AN_OBUF[3]} {AN_OBUF[4]} {AN_OBUF[5]} {AN_OBUF[6]} {AN_OBUF[7]}]]
+set_property port_width 48 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {realSdPlayer/slowSender/to_send[0]} {realSdPlayer/slowSender/to_send[1]} {realSdPlayer/slowSender/to_send[2]} {realSdPlayer/slowSender/to_send[3]} {realSdPlayer/slowSender/to_send[4]} {realSdPlayer/slowSender/to_send[5]} {realSdPlayer/slowSender/to_send[6]} {realSdPlayer/slowSender/to_send[7]} {realSdPlayer/slowSender/to_send[8]} {realSdPlayer/slowSender/to_send[9]} {realSdPlayer/slowSender/to_send[10]} {realSdPlayer/slowSender/to_send[11]} {realSdPlayer/slowSender/to_send[12]} {realSdPlayer/slowSender/to_send[13]} {realSdPlayer/slowSender/to_send[14]} {realSdPlayer/slowSender/to_send[15]} {realSdPlayer/slowSender/to_send[16]} {realSdPlayer/slowSender/to_send[17]} {realSdPlayer/slowSender/to_send[18]} {realSdPlayer/slowSender/to_send[19]} {realSdPlayer/slowSender/to_send[20]} {realSdPlayer/slowSender/to_send[21]} {realSdPlayer/slowSender/to_send[22]} {realSdPlayer/slowSender/to_send[23]} {realSdPlayer/slowSender/to_send[24]} {realSdPlayer/slowSender/to_send[25]} {realSdPlayer/slowSender/to_send[26]} {realSdPlayer/slowSender/to_send[27]} {realSdPlayer/slowSender/to_send[28]} {realSdPlayer/slowSender/to_send[29]} {realSdPlayer/slowSender/to_send[30]} {realSdPlayer/slowSender/to_send[31]} {realSdPlayer/slowSender/to_send[32]} {realSdPlayer/slowSender/to_send[33]} {realSdPlayer/slowSender/to_send[34]} {realSdPlayer/slowSender/to_send[35]} {realSdPlayer/slowSender/to_send[36]} {realSdPlayer/slowSender/to_send[37]} {realSdPlayer/slowSender/to_send[38]} {realSdPlayer/slowSender/to_send[39]} {realSdPlayer/slowSender/to_send[40]} {realSdPlayer/slowSender/to_send[41]} {realSdPlayer/slowSender/to_send[42]} {realSdPlayer/slowSender/to_send[43]} {realSdPlayer/slowSender/to_send[44]} {realSdPlayer/slowSender/to_send[45]} {realSdPlayer/slowSender/to_send[46]} {realSdPlayer/slowSender/to_send[47]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 1 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list CA_OBUF]]
+set_property port_width 8 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {realSdPlayer/dataHandler/buffer\\.dina[0]} {realSdPlayer/dataHandler/buffer\\.dina[1]} {realSdPlayer/dataHandler/buffer\\.dina[2]} {realSdPlayer/dataHandler/buffer\\.dina[3]} {realSdPlayer/dataHandler/buffer\\.dina[4]} {realSdPlayer/dataHandler/buffer\\.dina[5]} {realSdPlayer/dataHandler/buffer\\.dina[6]} {realSdPlayer/dataHandler/buffer\\.dina[7]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-set_property port_width 1 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list CB_OBUF]]
+set_property port_width 6 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {realSdPlayer/cmd[0]} {realSdPlayer/cmd[1]} {realSdPlayer/cmd[2]} {realSdPlayer/cmd[3]} {realSdPlayer/cmd[4]} {realSdPlayer/cmd[5]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
 set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list CC_OBUF]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {realSdPlayer/dataHandler/buffer\\.address_half}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
 set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list CD_OBUF]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {realSdPlayer/dataHandler/buffer\\.clka}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
 set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list CE_OBUF]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {realSdPlayer/dataHandler/buffer\\.ena}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
 set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list CF_OBUF]]
+connect_debug_port u_ila_0/probe11 [get_nets [list realSdPlayer/fast_clk]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
 set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list CG_OBUF]]
+connect_debug_port u_ila_0/probe12 [get_nets [list realSdPlayer/fast_clk_enable]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list realSdPlayer/read_command_listen]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list realSdPlayer/read_command_received]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list reset]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list realSdPlayer/sd_data]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list realSdPlayer/send_command_ready]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list realSdPlayer/send_command_start]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list realSdPlayer/slowSender/send_sd_cmd]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list realSdPlayer/slow_clk]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list realSdPlayer/stored_sd_cmd]]
 set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
 set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
 set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
@@ -44,7 +44,8 @@
    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
    <Option Name="BoardPart" Val=""/>
-    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+    <Option Name="ActiveSimSet" Val="sd_controller_tb"/>
    <Option Name="DefaultLib" Val="xil_defaultlib"/>
    <Option Name="ProjectType" Val="Default"/>
    <Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
@@ -60,7 +61,7 @@
    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
    <Option Name="EnableBDX" Val="FALSE"/>
    <Option Name="DSABoardId" Val="nexys-a7-100t"/>
-    <Option Name="WTXSimLaunchSim" Val="87"/>
+    <Option Name="WTXSimLaunchSim" Val="211"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,6 +92,27 @@
  <FileSets Version="1" Minor="32">
    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/lib/audio_buffer_interface.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/lib/sdvd_defs.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/audio/audio_buffer.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PPRDIR/design/debouncer.sv">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -119,6 +141,13 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
+      <File Path="$PPRDIR/design/modular_clock_gen.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PPRDIR/design/playback_controller.sv">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -126,6 +155,20 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
+      <File Path="$PPRDIR/design/audio/pwm.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sd/rom_sd.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
      <File Path="$PPRDIR/design/segment_display/seconds_display.sv">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
@@ -140,25 +183,55 @@
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PPRDIR/design/sdvd_defs.sv">
+      <File Path="$PPRDIR/lib/assertion_error.sv">
        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PPRDIR/design/audio/audio_buffer.sv">
+      <File Path="$PPRDIR/roms/roundabout.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/roms/even_flow_16.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sd/send_command.sv">
        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PPRDIR/design/audio/pwm.sv">
+      <File Path="$PPRDIR/design/sd/crc_gen.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sd/read_command.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sd/read_data.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sd/sd_controller.sv">
        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
@@ -169,6 +242,7 @@
        <Option Name="TopModule" Val="nexys_a7_top"/>
        <Option Name="TopAutoSet" Val="TRUE"/>
        <Option Name="VerilogDir" Val="$PPRDIR/design"/>
+        <Option Name="VerilogDir" Val="$PPRDIR/lib"/>
      </Config>
    </FileSet>
    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -260,16 +334,15 @@
    </FileSet>
    <FileSet Name="playback_controller_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/playback_controller_tb" RelGenDir="$PGENDIR/playback_controller_tb">
      <Filter Type="Srcs"/>
-      <File Path="$PPRDIR/verification/playback_controller_tb.sv">
+      <File Path="$PPRDIR/lib/sdvd_defs.sv">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
-      <File Path="$PPRDIR/design/sdvd_defs.sv">
+      <File Path="$PPRDIR/verification/playback_controller_tb.sv">
        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="implementation"/>
          <Attr Name="UsedIn" Val="simulation"/>
@@ -320,6 +393,243 @@
        <Option Name="xsim.simulate.runtime" Val="10s"/>
      </Config>
    </FileSet>
+    <FileSet Name="rom_sd_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/rom_sd_tb" RelGenDir="$PGENDIR/rom_sd_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/roms/testfile.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/sd/rom_sd_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/waveform_configs/rom_sd_waveform.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/roms/consecutive.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="rom_sd_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/rom_sd_waveform.wcfg"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pwm_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/pwm_tb" RelGenDir="$PGENDIR/pwm_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/audio/pwm_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="pwm_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="crc_gen_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/crc_gen_tb" RelGenDir="$PGENDIR/crc_gen_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/sd/rom_sd_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/sd/crc_gen_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/waveform_configs/crc_gen_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="crc_gen_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/crc_gen_tb_behav.wcfg"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="send_command_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/send_command_tb" RelGenDir="$PGENDIR/send_command_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/sd/send_command_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="send_command_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="read_command_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/read_command_tb" RelGenDir="$PGENDIR/read_command_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/sd/read_command_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/waveform_configs/read_command_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="read_command_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/read_command_tb_behav.wcfg"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="read_data_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/read_data_tb" RelGenDir="$PGENDIR/read_data_tb">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/sd/read_data_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/waveform_configs/read_data_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="read_data_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/read_data_tb_behav.wcfg"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sd_controller_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sd_controller_tb" RelGenDir="$PGENDIR/sd_controller_tb">
+      <File Path="$PPRDIR/verification/sd/sd_controller_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/verification/waveform_configs/sd_controller_tb_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="sd_controller_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/sd_controller_tb_behav.wcfg"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+        <Option Name="xsim.simulate.runtime" Val="1s"/>
+      </Config>
+    </FileSet>
  </FileSets>
  <Simulators>
    <Simulator Name="XSim">
@@ -345,9 +655,7 @@
  <Runs Version="1" Minor="22">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -355,11 +663,9 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
@@ -633,6 +939,135 @@
      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
      <RQSFiles/>
    </Run>
+    <Run Id="impl_1_copy_3" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_3" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_3" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
+        <ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_3_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="nexys_a7_top_timing_summary_init_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_3_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="nexys_a7_top_drc_opted_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_3_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="nexys_a7_top_timing_summary_opted_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_3_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="nexys_a7_top_timing_summary_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_3_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="nexys_a7_top_io_placed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_3_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="nexys_a7_top_utilization_placed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_3_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="nexys_a7_top_control_sets_placed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="verbose" Type="" Value="true"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_3_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_pre_placed.rpt_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_3_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="nexys_a7_top_incremental_reuse_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_3_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="nexys_a7_top_timing_summary_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_3_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="nexys_a7_top_timing_summary_postplace_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_3_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="nexys_a7_top_timing_summary_physopted_1.rpt" Version="1" Minor="0" IsDisabled="true">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_3_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_3_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="nexys_a7_top_drc_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_3_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="nexys_a7_top_methodology_drc_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_3_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="nexys_a7_top_power_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_3_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="nexys_a7_top_route_status_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_3_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="nexys_a7_top_timing_summary_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_3_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="nexys_a7_top_incremental_reuse_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_3_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="nexys_a7_top_clock_utilization_routed_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_3_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="nexys_a7_top_bus_skew_routed_1.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_3_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_timing_summary_postroute_physopted_1.rpt" Version="1" Minor="0">
+          <ReportConfigOption Name="max_paths" Type="" Value="10"/>
+          <ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_3_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="nexys_a7_top_bus_skew_postroute_physopted_1.rpt" Version="1" Minor="1">
+          <ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
+          <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+          <ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
+        </ReportConfig>
+        <ReportConfig DisplayName="implementation_log" Name="impl_1_copy_3_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="nexys_a7_top.vdi">
+          <ReportConfigOption Name="dummy_option" Type="string"/>
+        </ReportConfig>
+      </ReportStrategy>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
  </Runs>
  <Board/>
  <DashboardSummary Version="1" Minor="0">
@@ -1,13 +0,0 @@
-## Bugs I Found
-
-### Audio Buffer
- Forgot to assign to a delay counter
-
-### Debouncer
- Logic was fundamentally wrong
-
-### Display Converter
- Found a typo in a single digit
-
-### Low Freq Clock Gen
- Was initially trying to do modulo at max clock speed, failing timing
@@ -1,6 +1,18 @@
+/****
+ * audio_buffer.sv - holds a 2KiB audio buffer of 16-bit pcm audio
+ *                   samples (with pcm being the audio format we are using)
+ *
+ * @author: Waylon Cude, Dilanthi
+ * @date: 6/12/2025
+ *
+ * */
+
+//define used here because verilator needs it but vivado is smart enough
+//not to. 
 `ifdef VERILATOR
    `include "sdvd_defs.sv"
 `endif
+
 import sdvd_defs::SPEED;

 //this interfaces with block ram
@@ -12,9 +24,6 @@ module audio_buffer(
    input logic play, stop,
    input SPEED speed,

-    // Whether the current address being read from is in the upper or lower
-    // half of the 2KiB buffer
-    output logic address_half,

    // Whether the audio buffer is currently playing
    output logic playing,
@@ -23,11 +32,8 @@ module audio_buffer(
    output logic [15:0] sample,

    // Inputs for the memory buffer
-    input logic [10:0] addra,
-    input logic [7:0] dina,
-    input logic clka, ena
+    audio_buffer_interface.receiver driver
 );
-
 logic [9:0] address;

 // State register
@@ -37,8 +43,11 @@ logic [15:0] doutb;
 // A single bit counter, to avoid feeding samples given the 1 cycle read delay
 logic delay;

+// Whether the current address being read from is in the upper or lower
+// half of the 2KiB buffer
+//
 // The MSB of the address == higher/lower half address
-assign address_half = address[9];
+assign driver.address_half = address[9];

 always_ff @(posedge clk) begin
    enb <= 0;
@@ -66,8 +75,6 @@ always_ff @(posedge clk) begin
            // This will overflow to the correct value always
            address <= address + speed;
            enb <= 1;
-            // NOTE: I really don't know a good way to generate the load
-            // signal. It maybe could be an inverted 48khz clock?
            if (delay == 0) begin
                sample <= doutb;
            end
@@ -80,9 +87,7 @@ always_ff @(posedge clk) begin
    end
 end

-//xpm_memory_sdpram #(
-//    .WRITE_DATA_WIDTH_A(16)
-//) buffer ();
+//vivado block ram xpm macro
 xpm_memory_sdpram #(
  .ADDR_WIDTH_A(11),                    // DECIMAL
  .ADDR_WIDTH_B(10),                    // DECIMAL
@@ -117,30 +122,34 @@ xpm_memory_sdpram #(
 )
 buffer (
  .doutb(doutb),          // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
-  .addra(addra),          // ADDR_WIDTH_A-bit input: Address for port A write operations.
+  .addra(driver.addra),   // ADDR_WIDTH_A-bit input: Address for port A write operations.
  .addrb(address),        // ADDR_WIDTH_B-bit input: Address for port B read operations.
-  .clka(clka),            // 1-bit input: Clock signal for port A. Also clocks port B when
+  .clka(driver.clka),     // 1-bit input: Clock signal for port A. Also clocks port B when
                          // parameter CLOCKING_MODE is "common_clock".

  .clkb(clk),             // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                          // "independent_clock". Unused when parameter CLOCKING_MODE is
                          // "common_clock".
-  .dina(dina),            // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
-  .ena(ena),              // 1-bit input: Memory enable signal for port A. Must be high on clock
+  .dina(driver.dina),     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+  .ena(driver.ena),       // 1-bit input: Memory enable signal for port A. Must be high on clock
                          // cycles when write operations are initiated. Pipelined internally.

  .enb(enb),              // 1-bit input: Memory enable signal for port B. Must be high on clock
                          // cycles when read operations are initiated. Pipelined internally.
-//active high reset
  .rstb(reset),           // 1-bit input: Reset signal for the final port B output register stage.
                          // Synchronously resets output port doutb to the value specified by
                          // parameter READ_RESET_VALUE_B.
-  .wea(ena)               // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+  .wea(driver.ena),       // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                          // for port A input data port dina. 1 bit wide when word-wide writes are
                          // used. In byte-wide write configurations, each bit controls the
                          // writing one byte of dina to address addra. For example, to
                          // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                          // is 32, wea would be 4'b0010.
+  
+  .sleep(0),              // The XPM macros say these can be removed, but when I did this the
+  .injectsbiterra(0),     // entire block memory got optimized out. These were readded in later
+  .injectdbiterra(0),
+  .regceb(enb)
 );

 endmodule
@@ -1,8 +1,9 @@
 /****
- * pwm.sv - [must edit in future]
+ * pwm.sv - drives the pwm audio output on the FPGA given a single 16-bit
+ *          sample. 
 *
 * @author: Dilanthi Prentice, Waylon Cude
- * @date: [not sure when due yet]
+ * @date: 6-12-2025
 *
 *
 * */
@@ -15,8 +16,11 @@ module pwm(
    // The audio output pin
    output wire pwm_pin
 );
+// This  can't be 16 or we are slowing the audio rate down by a factor of
+// 2^5=32
+parameter DEPTH=11;

-logic [15:0] pulse_counter;
+logic [DEPTH-1:0] pulse_counter;
 logic [15:0] sample_buffer;
 logic should_output;

@@ -26,6 +30,7 @@ begin
    begin
        pulse_counter <= 0;
        sample_buffer <= 0;
+        should_output <= 0;
    end
    
    else
@@ -35,7 +40,7 @@ begin
        
        pulse_counter <= pulse_counter + 1;

-        if (pulse_counter < sample_buffer)
+        if (pulse_counter < sample_buffer[15-:DEPTH])
            should_output <= 1;
        else
            should_output <= 0;
@@ -1,3 +1,11 @@
+/***
+ * debouncer.sv - generates a debounced button press and turns it into
+ *                a single pulse.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6-12-25
+ *
+ * */
 //NOTE: you should drive this with a slow clock to actually debounce input
 module debouncer(input logic clk, input reset, input source, output logic out);

@@ -1,3 +1,12 @@
+/****
+ * low_freq_clock_gen.sv - Generates different clock frequencies to drive
+ *                         different state machines and different parts of
+ *                         the design. 
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ * */
+//Define used because verilator needs it but vivado is samrt enough not to
 `ifdef VERILATOR
    `include "sdvd_defs.sv"
 `endif
@@ -10,7 +19,7 @@ module low_freq_clock_gen(
    output logic clk1k, clk10h, seconds_pulse
 );

-// Hardcoded to be 1,000,000/4,000
+// Hardcoded to be 1,000,000/4,000 (25,000)
 // Relying on constant maths makes it the wrong size
 localparam num_cycles = 25_000;

@@ -0,0 +1,34 @@
+/****
+ * modular_clock_gen.sv - parameterizable clock divider.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * */
+module modular_clock_gen(
+    input clk, reset,
+    output logic oclk
+);
+//parameter has no default because the user should always set it
+parameter DIVISOR;
+
+logic [$clog2(DIVISOR)-1:0] counter;
+
+logic set;
+
+always_ff @(posedge clk) begin
+    // modular clock has to keep ticking through reset
+    // so everything with a synchronous reset actually works
+    if (reset && !set) begin
+        counter <= DIVISOR-1;
+        set <= 1;
+    end
+    else if (counter == 0)
+        counter <= DIVISOR-1;
+    else 
+        counter <= counter - 1;
+
+    oclk <= counter < (DIVISOR/2);
+end
+
+endmodule
@@ -1,3 +1,10 @@
+/***
+ * nexys_a7_top.sv - top level design module specific to Nexys A7100T.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * **/
 `ifdef VERILATOR
    `include "sdvd_defs.sv"
 `endif
@@ -5,8 +12,14 @@ import sdvd_defs::SPEED;
 module nexys_a7_top(
    input logic CLK100MHZ, CPU_RESETN,
    input logic BTNC, BTNR,
+    output logic AUD_PWM, AUD_SD,
    output logic CA,CB,CC,CD,CE,CF,CG,
-    output logic [7:0] AN
+    output logic [7:0] AN,
+    output wire LED[0:0],
+    output wire SD_RESET,SD_SCK,
+    inout wire [3:0] SD_DAT,
+    inout wire SD_CMD,
+    input wire SD_CD
 );

 // Active high reset
@@ -14,10 +27,13 @@ wire reset;
 assign reset = ~CPU_RESETN;

 logic clk_1khz, clk_10hz;
+logic clk_48khz, clk_1mhz;
 logic seconds_pulse;

 SPEED speed;

+audio_buffer_interface audio_interface();
+
 // Map C{A-G} to an array of 7-segment displays
 wire [6:0] segments [7:0];
 wire [2:0] segment_mux_select;
@@ -25,18 +41,33 @@ wire [2:0] segment_mux_select;
 // These segments are currently unused
 assign segments[7] = 0;
 assign segments[6] = 0;
+// These are the ones we're using
 assign {CA,CB,CC,CD,CE,CF,CG} = ~segments[segment_mux_select];

 logic [$clog2(60)-1:0] seconds;
 logic [$clog2(60)-1:0] minutes;
 logic [$clog2(60)-1:0] hours;

-low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
+logic [15:0] audio_sample;
+logic sd_ready;
+logic playing;
+
+assign LED[0] = playing;
+assign AUD_SD = playing;
+
+low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, 'z, clk_10hz, seconds_pulse);
+
+modular_clock_gen #(100_000) anodeClock(CLK100MHZ, reset, clk_1khz);
+
+// Create a clock with a divisor of 2083, making ~48khz
+modular_clock_gen #(2083) audioClock(CLK100MHZ, reset, clk_48khz);
+modular_clock_gen #(100) pwmClock(CLK100MHZ, reset, clk_1mhz);
+

 // Count the number on seconds, hours, and minutes elapsed
 // If the speed is faster this will pulse more often than once a second
 // but will still theoretically be a second of video time
-always_ff @(posedge seconds_pulse) begin
+always_ff @(posedge seconds_pulse or posedge reset) begin
    if (reset) begin
        seconds <= 0;
        minutes <= 0;
@@ -65,8 +96,49 @@ seconds_display hoursSegment (hours, segments[5], segments[4]);
 // Gets rid of button bouncing
 playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);

+pwm audioOutput(CLK100MHZ, reset, clk_48khz, audio_sample, AUD_PWM);
+audio_buffer audioBuffer(
+    clk_48khz, 
+    reset, 
+    sd_ready, 
+    '0, // stop signal not used right now 
+    speed, 
+    playing,
+    audio_sample, 
+    audio_interface.receiver
+);

+`ifdef ROM
+    rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
+    assign {SD_RESET,SD_DAT,SD_CMD,SD_SCK} = 'z;
+`else
+    // Power the sd slot
+    assign SD_RESET = 0;
+    // We don't use more than one dat line
+    assign SD_DAT[3:1] = 'z;
+    logic clk_100khz;
+    logic clk_25mhz;
+    // We can clock this at around 200khz before things start breaking
+    // Even at 200khz sometimes things break
+    modular_clock_gen #(1000) slowSdClock(CLK100MHZ, reset, clk_100khz);
+    // Try clocking this slower than max speed
+    // To see if that makes it actually work 
+    //
+    // NOTE: It did not make it work
+    modular_clock_gen #(1000) fastSdClock(CLK100MHZ, reset, clk_25mhz);
+    sd_controller realSdPlayer(
+        clk_100khz,
+        clk_25mhz,
+        CLK100MHZ,
+        reset,
+        SD_DAT[0],
+        SD_CMD,
+        sd_ready,
+        SD_SCK,
+        audio_interface.driver
+    );

+`endif


 endmodule
@@ -9,6 +9,8 @@
 *
 * */

+//VERILATOR define used here because verilator needs it to find the package
+//while vivado is smart enough not to.
 `ifdef VERILATOR
    `include "sdvd_defs.sv"
 `endif
@@ -35,7 +37,6 @@ state_t current, next;

 wire play_pulse,ff_pulse;

-// NOTE: These might need to be hooked to an even lower clock? Not sure
 debouncer playDebouncer (clk,reset,play,play_pulse);
 debouncer ffDebouncer (clk,reset,ff,ff_pulse);

@@ -0,0 +1,47 @@
+/***
+ * crc_gen.sv - paramerizable sequential crc generator. This could probably be
+ *              combinational logic too (but it would be way slower)
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * */
+module crc_gen #(
+    parameter CRCBITS=7,
+    parameter COMMANDLEN=40,
+    parameter POLYNOMIAL='h89
+) (
+    input clk,
+    input reset,
+    input start,
+    input [COMMANDLEN-1:0] num,
+    output logic ready,
+    output logic [CRCBITS-1:0] crc
+);
+
+logic [$clog2(COMMANDLEN):0] counter;
+logic [COMMANDLEN+CRCBITS-1:0] div_reg;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        counter <= 0;
+        crc <= 0;
+    end
+    else if (start) begin
+        counter <= COMMANDLEN;
+        div_reg <= {num, {CRCBITS{1'b0}}};
+        ready <= 0;
+    end
+    else if (counter != 0) begin
+        if (div_reg[counter+CRCBITS-1] == 1) begin
+            div_reg <= div_reg ^ (POLYNOMIAL << (counter-1));
+        end
+        counter <= counter - 1;
+    end
+    else begin
+        ready <= 1;
+        crc <= div_reg[CRCBITS-1:0];
+    end
+end
+
+endmodule
@@ -0,0 +1,138 @@
+/****
+ * read_command.sv - reads the sd command line and listens for sd command
+ *                   responses.
+ * 
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * **/
+module read_command(
+    input logic clk,
+    input logic reset,
+    input logic listen,
+    // 8 types of responses??? so hard to tell
+    input logic[2:0] response_type,
+    input logic sd_cmd,
+    output logic received,
+    // This has to be large enough to capture each possible response
+    output logic [135:0] out_data
+);
+
+enum logic [2:0] {IDLE,START,LISTEN,RECEIVING,DONE} state, next_state;
+
+// This should be large enough to capture the largest 136-bit response
+logic [$clog2(136):0] counter;
+logic [135:0] data_reg;
+logic received_reg;
+
+logic [2:0] response_type_reg;
+
+// recevied was set a cycle before the data was actually ready
+// and if it's just a register it holds for too long
+// use both for maximum reactivity
+assign received = received_reg && !listen;
+
+always_comb begin
+    case (state)
+        IDLE:
+            if (listen)
+                next_state=START;
+            else
+                next_state=IDLE;
+        START:
+            if (sd_cmd == 0)
+                next_state=RECEIVING;
+            else
+                next_state=LISTEN;
+        LISTEN:
+            // check for the start bit
+            if (sd_cmd == 0)
+                next_state=RECEIVING;
+            else
+                next_state=LISTEN;
+        RECEIVING:
+            if (counter == 0)
+                next_state=DONE;
+            else
+                next_state=RECEIVING;
+        DONE:
+            if (listen)
+                next_state=START;
+            else
+                next_state=DONE;
+        default:
+            next_state=IDLE;
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    case (state)
+        IDLE:
+        begin
+            // This defaulted to 1 ... oops
+            received_reg <= 0;
+            out_data <= 0;
+            if (listen)
+                response_type_reg <= response_type;
+        end
+
+        START:
+        begin
+            received_reg <= 0;
+            // off-by-one/cycle timing issues accumulated to a counter offset
+            // of 3.
+            // 3 in simulation, 2 in reality????
+            counter <= get_bits(response_type_reg) - 2;
+            data_reg <= 0;
+        end
+
+        LISTEN: 
+            // This is kinda a hack
+            // I don't fully understand why the receiving state misses two
+            // whole bits, I get why it misses the first but not the second...
+            data_reg[0] <= sd_cmd;
+
+        RECEIVING:
+        begin
+            counter <= counter - 1;
+            data_reg <= {data_reg[134:0],sd_cmd};
+        end
+
+        DONE:
+        begin
+            out_data <= data_reg;
+            received_reg <= 1;
+            if (listen) begin
+                received_reg <= 0;
+                response_type_reg <= response_type;
+            end
+        end
+
+        default: ;
+
+    endcase
+
+end
+
+always_ff @(posedge clk) begin
+    if (reset)
+        state<=IDLE;
+    else
+        state<=next_state;
+end
+
+
+function automatic logic [$clog2(136):0] get_bits(logic [2:0] response);
+    case (response)
+        // Response 2 is extra long
+        2: 
+            return 136;
+        // Most responses are 48 bits
+        default:
+            return 48;
+    endcase
+endfunction
+
+
+
+endmodule
@@ -0,0 +1,71 @@
+/***
+ * read_data.sv - whenever we receive a data block, start spitting bytes out
+ *                into the audio buffer block ram. This could be clocked at
+ *                25MHz default speed clock, or it could swtich over like the
+ *                writer has to.
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ ***/
+module read_data(
+    input clk,
+    input reset,
+    input sd_data,
+    (* MARK_DEBUG = "TRUE" *)
+    audio_buffer_interface.driver buffer
+);
+//  Block data is a start bit, 512 bytes sent msb first, then a CRC16 and end
+//  bit.
+
+// NOTE: This doesn't check which side of the buffer the audio player is
+// reading from, so theoretically it could overwrite audio that's being
+// played. However, as long as the sd card controller doesn't request extra
+// blocks this shouldn't be an issue
+
+localparam BLOCK_SIZE=512*8+16+2;
+logic [$clog2(BLOCK_SIZE):0] counter;
+
+logic [7:0] byte_shift;
+
+logic [3:0] byte_counter;
+
+assign buffer.clka = clk;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        buffer.ena <= 0;
+        buffer.addra <= '1;
+        buffer.dina <= 0;
+    end
+    else begin
+        // We ignore the lower 17 bits of the block
+        if (counter > 16) begin
+            counter <= counter - 1;
+            byte_shift <= {byte_shift[6:0],sd_data};
+            byte_counter <= byte_counter - 1;
+
+            // Store received byte in audio buffer and reset counter
+            if (byte_counter == 0) begin
+                byte_counter <= 7;
+                buffer.dina <= byte_shift;//{byte_shift[6:0],sd_data};
+                buffer.ena <= 1;
+            end
+
+            // Turn the enable signal off so we don't accidentally write
+            // anything weird
+            if (byte_counter == 4) begin
+                buffer.ena <= 0;
+                buffer.addra <= buffer.addra + 1;
+            end
+
+        end
+        else if (counter != 0)
+            counter<=counter-1;
+        else if (sd_data == 0) begin
+            counter <= BLOCK_SIZE-1;
+            byte_counter <= 8;
+        end
+    end
+end
+
+endmodule
@@ -0,0 +1,172 @@
+/****
+ * rom_sd.sv - reads audio data off a rom and feeds it to the audio buffer
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/25
+ *
+ * **/
+module rom_sd(
+    input logic clk,
+    input logic reset,
+    output logic ready,
+
+    audio_buffer_interface.driver buffer
+);
+parameter MEM_FILE = "roundabout.mem";
+
+typedef enum logic [3:0]{
+    RESET, DELAY1, DELAY2, DELAY3, WRITEBUF, ENDWRITE1, ENDWRITE2, ENDWRITE3, WAIT
+} state_t;
+
+state_t current, next;
+// First we write 2048B into the memory buffer, then signal to play it and
+// wait for half signal to avoid overwriting memory
+logic [18:0] rom_addr;
+logic [7:0] rom_data;
+logic rom_enable;
+logic buffer_half;
+
+
+// xpm_memory_sprom: Single Port ROM
+// Xilinx Parameterized Macro, version 2024.2
+
+// The ROM has 17 address bits and 8 data bits to store 128KiB, more than
+// enough for one second of 48khz audio
+xpm_memory_sprom #(
+  .ADDR_WIDTH_A(19),               // DECIMAL
+  .AUTO_SLEEP_TIME(0),             // DECIMAL
+  .CASCADE_HEIGHT(0),              // DECIMAL
+  .ECC_BIT_RANGE("7:0"),           // String
+  .ECC_MODE("no_ecc"),             // String
+  .ECC_TYPE("none"),               // String
+  .IGNORE_INIT_SYNTH(0),           // DECIMAL
+  .MEMORY_INIT_FILE(MEM_FILE),     // String
+  .MEMORY_INIT_PARAM(""),         // String
+  .MEMORY_OPTIMIZATION("true"),    // String
+  .MEMORY_PRIMITIVE("auto"),       // String
+  .MEMORY_SIZE((1<<19)*8),          // DECIMAL
+  .MESSAGE_CONTROL(0),             // DECIMAL
+  .RAM_DECOMP("auto"),             // String
+  .READ_DATA_WIDTH_A(8),           // DECIMAL
+  .READ_LATENCY_A(2),              // DECIMAL
+  .READ_RESET_VALUE_A("0"),        // String
+  .RST_MODE_A("SYNC"),             // String
+  .SIM_ASSERT_CHK(0),              // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .USE_MEM_INIT(1),                // DECIMAL
+  .USE_MEM_INIT_MMI(0),            // DECIMAL
+  .WAKEUP_TIME("disable_sleep")    // String
+)
+xpm_memory_sprom_inst (
+  .douta(rom_data),                // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+  .addra(rom_addr),                // ADDR_WIDTH_A-bit input: Address for port A read operations.
+  .clka(clk),                      // 1-bit input: Clock signal for port A.
+  .ena(rom_enable),                // 1-bit input: Memory enable signal for port A. Must be high on clock
+                                   // cycles when read operations are initiated. Pipelined internally.
+
+  .rsta(reset),                     // 1-bit input: Reset signal for the final port A output register stage.
+                                   // Synchronously resets output port douta to the value specified by
+                                   // parameter READ_RESET_VALUE_A.
+                                   
+  // These are required I think? The ROM gets optimized out without them
+  .sleep(0),
+  // Should this have a separate control signal? What happens if it gets
+  // turned on early like I'm doing now?
+  .regcea(rom_enable),
+  .injectsbiterra(0),
+  .injectdbiterra(0)
+);
+// End of xpm_memory_sprom_inst instantiation
+
+assign buffer_half = buffer.addra[10];
+// The audio buffer memory is clocked at the same speed as this module
+assign buffer.clka = clk;
+
+//next state logic
+always_comb
+begin
+    case (current)
+        RESET:      if (reset) next = RESET;
+                    else next = DELAY1;
+        DELAY1:     next = DELAY2;
+        DELAY2:     next = DELAY3;
+        DELAY3:     next = WRITEBUF;
+        
+        WRITEBUF:   if (buffer.addra[9:0] < 1020) next = WRITEBUF;
+                    else next = ENDWRITE1;
+        
+        ENDWRITE1:   next = ENDWRITE2;
+        ENDWRITE2:   next = ENDWRITE3;
+        ENDWRITE3:   next = WAIT;
+        
+        WAIT:       if (buffer_half == buffer.address_half) next = WAIT;
+                    else next = DELAY1;
+        
+        default: next = RESET;
+    endcase
+end
+
+//sequential output logic
+always_ff @(posedge clk)
+begin
+    case (current)
+        RESET:      begin
+                    rom_addr <= 0;
+                    rom_enable <= 1;
+                    buffer.addra <= 0;
+                    buffer.ena <= 0;
+                    ready <= 0;
+                    end
+        
+        DELAY1:     rom_addr <= rom_addr + 1;
+        DELAY2:     rom_addr <= rom_addr + 1;
+        DELAY3:     begin
+                    rom_addr <= rom_addr + 1;
+                    buffer.dina <= rom_data;
+                    buffer.ena <= 1;
+                    end
+        
+        WRITEBUF:   begin
+                    buffer.ena <= 1;
+                    buffer.dina <= rom_data;
+                    buffer.addra <= buffer.addra + 1;
+                    rom_addr <= rom_addr + 1;
+                    end
+
+        ENDWRITE1, ENDWRITE2:   
+                    begin
+                    buffer.ena <= 1;
+                    buffer.dina <= rom_data;
+                    buffer.addra <= buffer.addra + 1;
+                    end
+
+        
+        ENDWRITE3:  begin
+                    buffer.ena <= 0;
+                    buffer.dina <= rom_data;
+                    buffer.addra <= buffer.addra + 1;
+                    ready <= 1;
+                    end
+        
+        WAIT:       ;
+        
+        default:    begin
+                    rom_addr <= 0;
+                    rom_enable <= 0; 
+                    buffer.addra <= 0;
+                    buffer.dina <= 0;
+                    buffer.ena <= 0;
+                    ready <= 0;
+                    end
+    endcase
+end
+
+//sequential clocking block
+always_ff @(posedge clk)
+begin
+    if (reset)
+        current <= RESET;
+    else
+        current <= next;
+end
+
+endmodule
@@ -0,0 +1,391 @@
+/****
+ * sd_controller.sv - Initializes and reads data off an sd card, feeding it
+ *                    into the audio buffer
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/25
+ *
+ * **/
+module sd_controller(
+(* MARK_DEBUG = "TRUE" *)
+    input logic slow_clk,
+(* MARK_DEBUG = "TRUE" *)
+    input logic fast_clk,
+    input logic crc_clk,
+    input logic reset,
+(* MARK_DEBUG = "TRUE" *)
+    input logic sd_data,
+    inout logic sd_cmd,
+    output logic ready,
+    output wire clk,
+
+    audio_buffer_interface.driver buffer
+);
+// NOTE: this gets encoded as one-hot, even if in here I set it as a logic[5:0]
+(* MARK_DEBUG = "TRUE" *)
+enum logic [5:0] {
+    INIT,WAIT,SEND_CMD0,WAIT_CMD0,DELAY_CMD0, // last 4
+    SEND_CMD8,WAIT_CMD8,LISTEN_RESPONSE_CMD8,WAIT_RESPONSE_CMD8, // last 8
+    SEND_CMD55,WAIT_CMD55,LISTEN_RESPONSE_CMD55,WAIT_RESPONSE_CMD55, // last 12
+    SEND_ACMD41,WAIT_ACMD41,LISTEN_RESPONSE_ACMD41,WAIT_RESPONSE_ACMD41,ACMD41_DELAY, //17
+    SEND_CMD2,WAIT_CMD2,LISTEN_RESPONSE_CMD2,WAIT_RESPONSE_CMD2, //21
+    SEND_CMD3,WAIT_CMD3,LISTEN_RESPONSE_CMD3,WAIT_RESPONSE_CMD3, //25
+    SEND_CMD7,WAIT_CMD7,LISTEN_RESPONSE_CMD7,WAIT_RESPONSE_CMD7, //29
+    READY_TO_TRANSMIT,
+    TRANSMIT,WAIT_TRANSMIT,WAIT_END,FINISH_TRANSMIT,
+    TRANSMIT2,WAIT_TRANSMIT2,WAIT_END2,FINISH_TRANSMIT2,
+    WAIT_FOR_BUFFER
+    } state, next_state;
+
+(* MARK_DEBUG = "TRUE" *)
+logic fast_clk_enable;
+assign clk = fast_clk_enable ? fast_clk : slow_clk;
+
+logic [$clog2(4114):0] counter;
+logic sd_buffer_half;
+logic [31:0] address;
+
+(* MARK_DEBUG = "TRUE" *)
+logic send_command_start;//, send_command_start_fast;
+(* MARK_DEBUG = "TRUE" *)
+logic [5:0] cmd;
+(* MARK_DEBUG = "TRUE" *)
+logic [31:0] arg;
+(* MARK_DEBUG = "TRUE" *)
+wire send_command_ready;//, send_command_ready_fast;
+
+(* MARK_DEBUG = "TRUE" *)
+logic stored_sd_cmd;
+
+// This needs to swap speeds
+send_command slowSender(
+    clk,
+    crc_clk,
+    reset,
+    send_command_start,
+    cmd,
+    arg,
+    send_command_ready,
+    sd_cmd);
+
+//send_command fastSender(
+//    fast_clk,
+//    crc_clk,
+//    reset,
+//    send_command_start_fast,
+//    cmd,
+//    arg,
+//    send_command_ready_fast,
+//    sd_cmd);
+
+(* MARK_DEBUG = "TRUE" *)
+logic read_command_listen;
+logic [2:0] response_type;
+(* MARK_DEBUG = "TRUE" *)
+wire read_command_received;
+wire [135:0] out_data;
+
+// Hopefully this doesn't get optimized out...
+(* MARK_DEBUG = "TRUE" *)
+logic [47:0] received_data;
+assign received_data = out_data[47:0];
+
+// This doesn't need to swap speeds as we ignore responses to CMD17
+read_command slowReader(
+    slow_clk,
+    reset,
+    read_command_listen,
+    response_type,
+    sd_cmd,
+    read_command_received,
+    out_data
+);
+
+// The data line is only ever used at fast_clk speeds
+read_data dataHandler(
+    fast_clk,
+    reset,
+    sd_data,
+    buffer
+);
+
+//always_ff @(posedge crc_clk) begin
+//    stored_sd_cmd <= sd_cmd;
+//end
+
+// Next state logic
+always_comb begin
+    case (state)
+        INIT: next_state=WAIT;
+        WAIT: 
+            if (counter==0)
+                next_state=SEND_CMD0;
+            else
+                next_state=WAIT;
+        SEND_CMD0:
+            next_state=WAIT_CMD0;
+        WAIT_CMD0:
+            if (send_command_ready)
+                next_state=DELAY_CMD0;
+            else
+                next_state=WAIT_CMD0;
+        DELAY_CMD0:
+            if (counter == 0)
+                next_state=SEND_CMD8;
+            else
+                next_state=DELAY_CMD0;
+        // These state transitions are all very similar, this probably could
+        // be a macro
+        SEND_CMD8:
+            next_state=WAIT_CMD8;
+        WAIT_CMD8:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD8;
+            else
+                next_state=WAIT_CMD8;
+        LISTEN_RESPONSE_CMD8:
+            next_state=WAIT_RESPONSE_CMD8;
+        WAIT_RESPONSE_CMD8:
+            if (read_command_received)
+                next_state=SEND_CMD55;
+            else
+                next_state=WAIT_RESPONSE_CMD8;
+        SEND_CMD2:
+            next_state=WAIT_CMD2;
+        WAIT_CMD2:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD2;
+            else
+                next_state=WAIT_CMD2;
+        LISTEN_RESPONSE_CMD2:
+            next_state=WAIT_RESPONSE_CMD2;
+        WAIT_RESPONSE_CMD2:
+            if (read_command_received)
+                next_state=SEND_CMD3;
+            else
+                next_state=WAIT_RESPONSE_CMD2;
+        SEND_CMD3:
+            next_state=WAIT_CMD3;
+        WAIT_CMD3:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD3;
+            else
+                next_state=WAIT_CMD3;
+        LISTEN_RESPONSE_CMD3:
+            next_state=WAIT_RESPONSE_CMD3;
+        WAIT_RESPONSE_CMD3:
+            if (read_command_received)
+                next_state=SEND_CMD7;
+            else
+                next_state=WAIT_RESPONSE_CMD3;
+        SEND_CMD7:
+            next_state=WAIT_CMD7;
+        WAIT_CMD7:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD7;
+            else
+                next_state=WAIT_CMD7;
+        LISTEN_RESPONSE_CMD7:
+            next_state=WAIT_RESPONSE_CMD7;
+        WAIT_RESPONSE_CMD7:
+            if (read_command_received)
+                next_state=READY_TO_TRANSMIT;
+            else
+                next_state=WAIT_RESPONSE_CMD7;
+
+        
+        SEND_CMD55:
+            next_state=WAIT_CMD55;
+        WAIT_CMD55:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD55;
+            else
+                next_state=WAIT_CMD55;
+        LISTEN_RESPONSE_CMD55:
+            next_state=WAIT_RESPONSE_CMD55;
+        WAIT_RESPONSE_CMD55:
+            if (read_command_received)
+                next_state=SEND_ACMD41;
+            else
+                next_state=WAIT_RESPONSE_CMD55;
+        SEND_ACMD41:
+            next_state=WAIT_ACMD41;
+        WAIT_ACMD41:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_ACMD41;
+            else
+                next_state=WAIT_ACMD41;
+        LISTEN_RESPONSE_ACMD41:
+            next_state=WAIT_RESPONSE_ACMD41;
+        WAIT_RESPONSE_ACMD41:
+            if (read_command_received && !out_data[39])
+                next_state=ACMD41_DELAY;
+            else if (read_command_received && out_data[39])
+                next_state=SEND_CMD2;
+            else
+                next_state=WAIT_RESPONSE_ACMD41;
+        ACMD41_DELAY:
+            if (counter == 0)
+                next_state=SEND_CMD55;
+            else
+                next_state=ACMD41_DELAY;
+
+        READY_TO_TRANSMIT:
+            next_state=TRANSMIT;
+        TRANSMIT:
+            next_state=WAIT_TRANSMIT;
+        WAIT_TRANSMIT:
+            if (sd_data==0)
+                next_state=WAIT_END;
+            else
+                next_state=WAIT_TRANSMIT;
+        WAIT_END:
+            if (counter==0)
+                next_state=FINISH_TRANSMIT;
+            else
+                next_state=WAIT_END;
+        FINISH_TRANSMIT:
+            next_state=TRANSMIT2;
+        TRANSMIT2:
+            next_state=WAIT_TRANSMIT2;
+        WAIT_TRANSMIT2:
+            if (sd_data==0)
+                next_state=WAIT_END2;
+            else
+                next_state=WAIT_TRANSMIT2;
+        WAIT_END2:
+            if (counter==0)
+                next_state=FINISH_TRANSMIT2;
+            else
+                next_state=WAIT_END2;
+        FINISH_TRANSMIT2:
+            next_state=WAIT_FOR_BUFFER;
+
+        WAIT_FOR_BUFFER:
+            if (sd_buffer_half==buffer.address_half)
+                next_state=WAIT_FOR_BUFFER;
+            else
+                next_state=TRANSMIT;
+        default:
+            next_state=INIT;
+    endcase
+
+end
+// This could mostly swap speeds ... however detecting the data line going low
+// would not work
+always_ff @(posedge clk) begin
+    stored_sd_cmd <= sd_cmd;
+    // Transition states
+    if (reset)
+        state <= INIT;
+    else
+        state <= next_state;
+
+    // Sequential outputs/logic
+    case (state)
+        INIT: begin
+            counter <= 80;
+            fast_clk_enable <= 0;
+        end
+        SEND_CMD0: begin
+            cmd<=0;
+            arg<=0;
+            send_command_start <= 1;
+        end
+        WAIT_CMD0: begin
+            counter<=20;
+            send_command_start<=0;
+        end
+        SEND_CMD8: begin
+            cmd <=8;
+            arg <='h1AA;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD8: begin
+            response_type <= 7;
+            read_command_listen <= 1;
+        end
+        SEND_CMD55: begin
+            cmd <= 55;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD55: begin
+            response_type <= 1;
+            read_command_listen <= 1;
+        end
+        SEND_ACMD41: begin
+            cmd <= 41;
+            arg <= 'h40100000;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_ACMD41: begin
+            response_type <= 3;
+            read_command_listen <= 1;
+        end
+        WAIT_RESPONSE_ACMD41: begin
+            read_command_listen<=0;
+            counter<=100;
+        end
+        SEND_CMD2: begin
+            cmd <= 2;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD2: begin
+            response_type <= 2;
+            read_command_listen <= 1;
+        end
+        SEND_CMD3: begin
+            cmd <= 3;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD3: begin
+            response_type <= 6;
+            read_command_listen <= 1;
+        end
+        SEND_CMD7: begin
+            cmd <= 7;
+            arg <= {out_data[39:24],16'h0000};
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD7: begin
+            response_type <= 1;
+            read_command_listen <= 1;
+        end
+        READY_TO_TRANSMIT: begin
+            fast_clk_enable <= 1;
+            address <= 0;
+            sd_buffer_half <= 0;
+        end
+        TRANSMIT, TRANSMIT2: begin
+            cmd <= 17;
+            arg <= address;
+            send_command_start <= 1;
+        end
+        WAIT_TRANSMIT, WAIT_TRANSMIT2: begin
+            send_command_start <= 0;
+            counter <= 411;
+        end
+        FINISH_TRANSMIT:
+            address <= address +1;
+        FINISH_TRANSMIT2: begin
+            address <= address +1;
+            sd_buffer_half <= ~sd_buffer_half;
+        end
+        WAIT_FOR_BUFFER:
+            ready <= 1;
+        // The logic is simple enough in these to group them
+        WAIT, DELAY_CMD0, ACMD41_DELAY, WAIT_END, WAIT_END2:
+            counter <= counter - 1;
+        WAIT_CMD8,WAIT_CMD55,WAIT_ACMD41,WAIT_CMD2,WAIT_CMD3,WAIT_CMD7:
+            send_command_start<=0;
+        WAIT_RESPONSE_CMD8,WAIT_RESPONSE_CMD55,WAIT_RESPONSE_CMD2,WAIT_RESPONSE_CMD3,
+        WAIT_RESPONSE_CMD7:
+            read_command_listen<=0;
+        default: ;
+
+    endcase
+end
+endmodule
@@ -0,0 +1,113 @@
+/***
+ * send_command.sv - sends sd card commands. It takes in a command and an
+ *                   argument and will figure out the necessary crc. 
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * */
+module send_command(
+    input clk, 
+    // The crc should be clocked way faster than the sender
+    input crc_clk,
+    input reset,
+    input start,
+    input [5:0] command,
+    input [31:0] arguments,
+    output logic ready,
+    output wire sd_cmd
+);
+(* MARK_DEBUG = "TRUE" *)
+logic [47:0] to_send;
+
+logic crc_start;
+wire crc_ready;
+logic [6:0] crc;
+
+logic [$clog2(48):0] counter;
+
+(* MARK_DEBUG = "TRUE" *)
+logic send_sd_cmd;
+
+enum logic [2:0] {READY, SEND_CRC, DELAY, WAIT_CRC, SEND_DATA} cur_state, next_state;
+
+// We theoretically could speed up sd card initialization by hardcoding the
+// CRCs for it, but wasting an extra couple of cycles at 400khz shouldn't
+// really matter
+crc_gen crcGen(crc_clk,reset,crc_start,to_send[47-:40],crc_ready,crc);
+
+// State transitions
+always_comb begin
+    case (cur_state)
+        READY: 
+            if (start)
+                next_state = SEND_CRC;
+            else 
+                next_state = READY;
+        SEND_CRC:
+            next_state = DELAY;
+        DELAY:
+            next_state = WAIT_CRC;
+        WAIT_CRC:
+            if (crc_ready)
+                next_state = SEND_DATA;
+            else
+                next_state = WAIT_CRC;
+        SEND_DATA:
+            if (counter != 1)
+                next_state = SEND_DATA;
+            else
+                next_state = READY;
+        default:
+            next_state = READY;
+    endcase
+            
+end
+
+assign sd_cmd = send_sd_cmd ? 'z : 0;
+// BUG SPOTTED: Too slow, make the output more reactive
+//              Added start input check to achieve this
+assign ready = (cur_state == READY && !start);
+// Sequential logic
+always_ff @(posedge clk) begin
+    // Default to high-z
+    send_sd_cmd <= 1;
+
+    case (cur_state)
+        READY:
+        begin
+            counter <= 48;
+        end
+        SEND_CRC:
+        begin
+            to_send <= {1'b0, 1'b1, command, arguments, 8'b1};
+            crc_start <= 1;
+        end
+        
+        DELAY:
+            crc_start <= 0;
+        WAIT_CRC: 
+            to_send[7:1] <= crc;
+
+        SEND_DATA:
+        begin
+            counter <= counter - 1;
+            send_sd_cmd <= to_send[counter-1]; 
+        end
+
+        default: ;
+
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        cur_state <= READY;
+    end
+    else begin
+        cur_state <= next_state;
+    end
+end
+
+
+endmodule
@@ -1,15 +1,31 @@
-// NOTE: This expects to be driven with a 100khz clock
+/***
+ * display_anode_driver.sv - Turns on a single anode of a single digit at a time,
+ *                           rapidly rotating through all of them, generating
+ *                           a solid-looking display even though only one digit
+ *                           is on at a time.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6-12-2025
+ *
+ * */
+
+// NOTE: This expects to be driven with a 100khz clock but can be altered in
+// the nexys_a7_top.sv file.
 module display_anode_driver(
    input logic clk, 
    input logic reset, 
    output logic [7:0] AN, 
    output logic [2:0] mux_select);

+// Initialize this once, it can be free-running after
+logic started;
+
 // This is just a shift register that drives each anode individually
 always_ff @(posedge clk) begin
    if (reset) begin
        AN <= '1 - 1;
        mux_select <= 0;
+        started <= 1;
    end
    else begin
        AN <= {AN[6:0], AN[7]};
@@ -1,12 +1,12 @@
 /**
 * display_converter.sv - decodes a 5 bit digit input into its seven segment
 *                        display equivalent using a lookup table. Display can
-*                        do 0 - 9, A - F, individual segmentsm and special
+*                        do 0 - 9, A - F, individual segments and special
 *                        characters.  
+*
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6/12/25
 *
-*
 ****/
 module display_converter(
    input logic [4:0] digit, 
@@ -16,6 +16,7 @@ module display_converter(
 localparam ROM_SIZE=32;

 //ROM lookup table for seven segment display
+//blanks are unused space we could add characters to. 
 localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
    7'b1111110, //0
    7'b0000110, //1
@@ -54,6 +55,7 @@ localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
    7'b0000000, //blank
    7'b0000000  //blank
 };
+
 //use digit input to index segment_rom lookup table.
 assign segment = segment_rom[digit];

@@ -1,10 +1,13 @@
 /***
-* seconds_display.sv - convert a seconds counter to a seven segement display.
+* sixty_display.sv - converts a binary digit from zero to fifty-nine to its
+*                    ones and tens digits and then gets the seven segment
+*                    display equivalents of them.
 *
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6/12/25
 *
 */
+
 module seconds_display
 (
    input [$clog2(60)-1:0] seconds,
@@ -15,14 +18,14 @@ module seconds_display
 logic [4:0] ones_digit; 
 logic [4:0] tens_digit;

+//convert digit to ones and tens places
 always_comb
 begin
    ones_digit = seconds % 10;
    tens_digit = seconds / 10;
 end

-//instantiate the display_converter to convert the counter
-//to a seven segment display number
+//convert both ones and tens place digits to their seven segement equivalent
 display_converter ones (ones_digit, display_ones);
 display_converter tens (tens_digit, display_tens);

@@ -0,0 +1,49 @@
+## Bugs I Found
+
+### Audio Buffer
+- Forgot to assign to a delay counter
+
+### Debouncer
+- Logic was fundamentally wrong
+- Found multiple logic bugs with testbench and then assertions
+
+### Display Converter
+- Found a typo in a single digit
+
+### Low Freq Clock Gen
+- Was initially trying to do modulo at max clock speed, failing timing
+
+
+### sd_rom
+- ROM was getting totally optimized out and was doing nothing in simulation, and
+  didn't show up in synthesized design
+- Timing issues, ROM was one cycle slower than expected, latching takes an extra
+  cycle too, had to rework state machines, there are a bonus 2 delay states when
+  starting and ending writes
+
+### PWM
+- major design problems
+- clocked too slow
+- initial goal of 16-bit audio isn't feasible because 100MHz isn't fast enough
+  to pwm based on a 16-bit counter, would give a sample rate of 1.5khz
+
+### command_sender
+- output ready signal was delay a cycle because it was set by sequential logic,
+  detected in testing, changed it to a combinational output for 1 cycle speedup
+- counter was being set in multiple blocks, caught by synthesis
+- output phase too long, caught in hw
+
+### read_command
+- response_type was not getting correctly stored/set, breaking the module
+  entirely. Detected in testbench
+- off-by-one error detected in the counter
+
+### read_data
+- audio buffer address to write to was never changing, caught in simulation
+- some off-by-one errors in the byte shifting were found and corrected
+
+### modular_clock
+- stopped ticking on reset
+- meant that every module using these clocks w/ a synchronous reset would get
+  stuck and never reset
+- found during hw debugging
@@ -0,0 +1,23 @@
+digraph rom_sd {
+    Reset [shape = doublecircle, label = "RESET\nbuffer_half = 0\nrom_addr = 0\nrom_enable = 1\nbuffer.addra=0\nready=0"];
+    node [shape = circle];
+    Delay [label="DELAY\nrom_addr++"];
+    WriteBuf [label="WRITEBUF\nbuffer.ena=1\nbuffer.dina=rom_data\nbuffer.addra++\nrom_addr++"];
+    EndWrite [label="ENDWRITE\nbuffer.ena=1\nbuffer.data=rom_data\nbuffer.addra++\nready=1"];
+    Wait [label = "WAIT\nbuffer.ena=0"];
+
+    Reset -> Reset [label="reset"];
+    Reset -> Delay [label="!reset"];
+
+    Delay -> WriteBuf;
+
+    WriteBuf -> WriteBuf [label="buffer.addra < 1023"]
+    WriteBuf -> EndWrite [label="buffer.addra == 1023"]
+
+    EndWrite -> Wait;
+
+    Wait -> Wait [label = "buffer_half == buffer.address_half"]
+    Wait -> Delay [label = "buffer_half != buffer.address_half"]
+
+
+}
@@ -0,0 +1,136 @@
+digraph sd_controller {
+    // Rough steps
+    INIT [shape=doublecircle, label="INIT\ncounter=80\nclk_source=slow"];
+    node [shape=ellipse]
+    // Tick at slow speed (100khz? 400khz?) for 80 ticks
+    WAIT [label="WAIT\ncounter--"];
+    // Send CMD0 with arg 0
+    SEND_CMD0 [label="SEND_CMD0\ncmd=0\narg=0\nstart=1"];
+    // There is no response to CMD0, so tick for 20 more cycles then send CMD8
+    WAIT_CMD0 [label="WAIT_CMD0\ncounter=20\nstart=0"];
+    DELAY_CMD0 [label="DELAY_CMD0\ncounter--"];
+    // Send CMD8 
+    SEND_CMD8 [label="SEND_CMD8\ncmd=8\narg=0x1AA\nstart=1"];
+    WAIT_CMD8 [label="WAIT_CMD8\nstart=0"];
+    LISTEN_RESPONSE_CMD8 [label="LISTEN_RESPONSE_CMD8\nresponse_type=7\nread_command.listen=1"]
+    WAIT_RESPONSE_CMD8 [label="WAIT_RESPONSE_CMD8\nread_command.listen=0"];
+
+    INIT -> WAIT;
+    WAIT -> WAIT [label="counter!=0"];
+    WAIT -> SEND_CMD0 [label="counter==0"];
+    SEND_CMD0 -> WAIT_CMD0;
+    WAIT_CMD0 -> DELAY_CMD0 [label="send_command.ready"];
+    WAIT_CMD0 -> WAIT_CMD0 [label="!send_command.ready"]
+    DELAY_CMD0 -> DELAY_CMD0 [label="counter!=0"];
+    DELAY_CMD0 -> SEND_CMD8 [label="counter==0"]
+    SEND_CMD8 -> WAIT_CMD8;
+    WAIT_CMD8 -> WAIT_CMD8 [label="!send_command.ready"]
+    WAIT_CMD8 -> LISTEN_RESPONSE_CMD8 [label="send_command.ready"]
+    LISTEN_RESPONSE_CMD8 -> WAIT_RESPONSE_CMD8;
+    WAIT_RESPONSE_CMD8 -> WAIT_RESPONSE_CMD8 [label="!read_command.received"]
+
+    // Send CMD55+CMD41 with arg 40100000 until card is ready
+    SEND_CMD55 [label="SEND_CMD55\ncmd=55\narg=0\nstart=1"];
+    WAIT_CMD55 [label="WAIT_CMD55\nstart=0"];
+    LISTEN_RESPONSE_CMD55 [label="LISTEN_RESPONSE_CMD55\nresponse_type=1\nread_command.listen=1"]
+    WAIT_RESPONSE_CMD55 [label="WAIT_RESPONSE_CMD55\nread_command.listen=0"]
+    SEND_ACMD41 [label="SEND_ACMD41\ncmd=41\narg=0x40100000\nstart=1"];
+    WAIT_ACMD41 [label="WAIT_ACMD41\nstart=0"];
+    LISTEN_RESPONSE_ACMD41 [label="LISTEN_RESPONSE_ACMD41\nresponse_type=3\nread_command.listen=1"]
+    WAIT_RESPONSE_ACMD41 [label="WAIT_RESPONSE_ACMD41\nread_command.listen=0\ncounter=100"];
+    // Delay trying this again
+    ACMD41_DELAY [label="ACMD41_DELAY\ncounter--"];
+    // Card is ready when bit31 is high
+    
+    WAIT_RESPONSE_CMD8 -> SEND_CMD55 [label="read_command.received"]
+    SEND_CMD55 -> WAIT_CMD55;
+    WAIT_CMD55 -> WAIT_CMD55 [label="!send_command.ready"];
+    WAIT_CMD55 -> LISTEN_RESPONSE_CMD55 [label="send_command.ready"];
+    LISTEN_RESPONSE_CMD55 -> WAIT_RESPONSE_CMD55;
+    WAIT_RESPONSE_CMD55 -> WAIT_RESPONSE_CMD55 [label="!read_command.received"]
+    WAIT_RESPONSE_CMD55 -> SEND_ACMD41 [label="read_command.received"]
+    SEND_ACMD41 -> WAIT_ACMD41
+    WAIT_ACMD41 -> WAIT_ACMD41 [label="!send_command.ready"]
+    WAIT_ACMD41 -> LISTEN_RESPONSE_ACMD41[label="send_command.ready"]
+    LISTEN_RESPONSE_ACMD41 -> WAIT_RESPONSE_ACMD41
+    WAIT_RESPONSE_ACMD41 -> WAIT_RESPONSE_ACMD41 [label="!read_command.received"]
+    WAIT_RESPONSE_ACMD41 -> ACMD41_DELAY [label="read_command.received && !out_data[39]"]
+    ACMD41_DELAY -> ACMD41_DELAY [label="counter!=0"]
+    ACMD41_DELAY -> SEND_CMD55 [label="counter==0"]
+
+    
+    // CMD2 with argument 0, dont need response
+    SEND_CMD2 [label="SEND_CMD2\ncmd=2\narg=0\nsend_command.start=1"];
+    WAIT_CMD2 [label="WAIT_CMD2\nsend_command.start=0"];
+    LISTEN_RESPONSE_CMD2 [label="LISTEN_RESPONSE_CMD2\nresponse_type=2\nread_command.listen=1"];
+    WAIT_RESPONSE_CMD2 [label="WAIT_RESPONSE_CMD2\nread_command.listen=0"];
+
+    WAIT_RESPONSE_ACMD41 -> SEND_CMD2 [label="read_command.received && out_data[39]"]
+    SEND_CMD2 -> WAIT_CMD2;
+    WAIT_CMD2 -> WAIT_CMD2 [label="!send_command.ready"]
+    WAIT_CMD2 -> LISTEN_RESPONSE_CMD2 [label="send_command.ready"]
+    LISTEN_RESPONSE_CMD2 -> WAIT_RESPONSE_CMD2;
+    WAIT_RESPONSE_CMD2 -> WAIT_RESPONSE_CMD2 [label="!read_command.received"]
+
+    // CMD3 with argument 0 to get RCA
+    SEND_CMD3 [label="SEND_CMD3\ncmd=3\narg=0\nsend_command.start=1"];
+    WAIT_CMD3 [label="WAIT_CMD3\nsend_command.start=0"];
+    LISTEN_RESPONSE_CMD3 [label="LISTEN_RESPONSE_CMD3\nresponse_type=6\nread_command.listen=1"];
+    WAIT_RESPONSE_CMD3 [label="WAIT_RESPONSE_CMD3\nread_command.listen=0"];
+
+    WAIT_RESPONSE_CMD2 -> SEND_CMD3 [label="read_command.received"]
+    SEND_CMD3 -> WAIT_CMD3
+    WAIT_CMD3 -> WAIT_CMD3 [label="!send_command.ready"]
+    WAIT_CMD3 -> LISTEN_RESPONSE_CMD3 [label="send_command.ready"]
+    LISTEN_RESPONSE_CMD3 -> WAIT_RESPONSE_CMD3;
+    WAIT_RESPONSE_CMD3 -> WAIT_RESPONSE_CMD3 [label="!read_command.received"]
+
+    // CMD7 to select the correct card given the RCA
+    SEND_CMD7 [label="SEND_CMD7\ncmd=7\narg={out_data[39:24],16'h0000}\nsend_command.start=1"];
+    WAIT_CMD7 [label="WAIT_CMD7\nsend_command.start=0"];
+    LISTEN_RESPONSE_CMD7 [label="LISTEN_RESPONSE_CMD7\nresponse_type=1\nread_command.listen=1"];
+    WAIT_RESPONSE_CMD7 [label="WAIT_RESPONSE_CMD7\nread_command.listen=0"];
+
+    WAIT_RESPONSE_CMD3 -> SEND_CMD7[label="read_command.received"]
+    SEND_CMD7 -> WAIT_CMD7;
+    WAIT_CMD7 -> WAIT_CMD7 [label="!send_command.ready"]
+    WAIT_CMD7 -> LISTEN_RESPONSE_CMD7 [label="send_command.ready"]
+    LISTEN_RESPONSE_CMD7 -> WAIT_RESPONSE_CMD7;
+    WAIT_RESPONSE_CMD7 -> WAIT_RESPONSE_CMD7 [label="!read_command.ready"]
+
+
+    // Now we can finally read blocks with CMD17
+    // Swap over to the fast clock
+    READY_TO_TRANSMIT [label="READY_TO_TRANSMIT\nclk_source=fast\naddress=0\nbuffer_half=0"];
+    // There are two sets of states because we need to read two blocks at once
+    TRANSMIT [label="TRANSMIT\ncmd=17\narg=address\nsend_command.start=1"];
+    WAIT_TRANSMIT [label="WAIT_TRANSMIT\nsend_command.start=0\ncounter=4114"];
+    WAIT_END [label="WAIT_END\ncounter--"];
+    FINISH_TRANSMIT [label="FINISH_TRANSMIT\naddress++"]
+
+    TRANSMIT2 [label="TRANSMIT2\ncmd=17\narg=address\nsend_command.start=1"];
+    WAIT_TRANSMIT2 [label="WAIT_TRANSMIT2\nsend_command.start=0\ncounter=4114"];
+    WAIT_END2 [label="WAIT_END2\ncounter--"];
+    FINISH_TRANSMIT2 [label="FINISH_TRANSMIT2\naddress++\nsd_buffer_half=!sd_buffer_half"]
+
+    // Wait for the buffer to be free, then go back to TRANSMIT
+    WAIT_FOR_BUFFER [label="WAIT_FOR_BUFFER\nready=1"];
+
+    WAIT_RESPONSE_CMD7 -> READY_TO_TRANSMIT [label="read_command.ready"]
+    READY_TO_TRANSMIT -> TRANSMIT;
+    TRANSMIT -> WAIT_TRANSMIT;
+    WAIT_TRANSMIT -> WAIT_TRANSMIT [label="sd_data==1"]
+    WAIT_TRANSMIT -> WAIT_END [label="sd_data==0"]
+    WAIT_END -> WAIT_END [label="counter!=0"]
+    WAIT_END -> FINISH_TRANSMIT [label="counter==0"]
+    FINISH_TRANSMIT -> TRANSMIT2;
+    TRANSMIT2 -> WAIT_TRANSMIT2;
+    WAIT_TRANSMIT2 -> WAIT_TRANSMIT2 [label="sd_data==1"]
+    WAIT_TRANSMIT2 -> WAIT_END2 [label="sd_data==0"]
+    WAIT_END2 -> WAIT_END2 [label="counter!=0"]
+    WAIT_END2 -> FINISH_TRANSMIT2 [label="counter==0"]
+    FINISH_TRANSMIT2 -> WAIT_FOR_BUFFER;
+
+    WAIT_FOR_BUFFER -> WAIT_FOR_BUFFER [label="sd_buffer_half==audio_buffer.address_half"];
+    WAIT_FOR_BUFFER -> TRANSMIT [label="sd_buffer_half!=audio_buffer.address_half"];
+}
@@ -0,0 +1,18 @@
+interface audio_buffer_interface;
+    logic [10:0] addra;
+    logic [7:0] dina;
+    logic clka;
+    logic ena;
+    logic address_half;
+
+    modport driver (
+        output addra, dina, clka, ena,
+        input address_half
+    );
+
+    modport receiver (
+        input addra, dina, clka, ena,
+        output address_half
+    );
+
+endinterface
@@ -0,0 +1,5 @@
+for i in range(1,256):
+    print(hex(i))
+for i in range(0,10):
+    for i in range(0,256):
+        print(hex(i))
@@ -0,0 +1,57 @@
+/*****
+ * pwm_tb.sv - testbench for the pwm.sv module. 
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/2025
+ * */
+
+module pwm_tb;
+    bit clk, reset;
+
+    logic load;
+    wire pwm_pin;
+    logic [15:0] sample;
+
+    pwm dut (.*);
+
+    initial forever #10 clk = ~clk;
+
+    initial begin
+        reset = 1;
+        @(posedge clk);
+        @(posedge clk);
+        reset = 0;
+        load = 1;
+        sample = 0;
+        for (int i=0; i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 0)
+                else $error("Should be low at %d",i);
+        end
+        reset = 0;
+        load = 1;
+        sample = '1;
+        @(posedge clk)
+        for (int i=0; i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 'z)
+                else $error("Should be high at %d",i);
+        end
+
+        reset = 0;
+        load = 1;
+        // Should be about half on
+        sample = 1<<15;
+        @(posedge clk)
+        for (int i=0; i < (1<<15); i++) begin
+            @(posedge clk) assert (pwm_pin === 'z) 
+                else $error("Should be high at %d",i);
+        end
+        sample = 1<<15;
+        for (int i = (1  << 15); i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 0)
+                else $error("Should be low at %d",i);
+        end
+        $finish;
+
+    end
+
+endmodule
@@ -1,6 +0,0 @@
-/*****
- * pwn_tb.sv - testbench for the pwn.sv module. 
- *
- * @author: Dilanthi Prentice, Waylon Cude
- * @date: 6/12/2025
- * */
@@ -0,0 +1,49 @@
+module crc_gen_tb;
+    parameter CRCBITS=7;
+    parameter COMMANDLEN=40;
+    parameter POLYNOMIAL='h89;
+
+    logic clk, reset, start, ready;
+    logic [COMMANDLEN-1:0] num;
+    logic [CRCBITS-1:0] crc;
+
+    logic [CRCBITS-1:0] test_cases [logic [COMMANDLEN-1:0]];
+
+    crc_gen #(CRCBITS,COMMANDLEN,POLYNOMIAL) dut (.*);
+
+    initial begin
+        clk = 0;
+        forever #10 clk = ~clk;
+    end
+
+    initial begin
+        test_cases = '{
+            'h1234567890: 'h10,
+            'hBEEFB05535: 'h05,
+            'h5544992211: 'h17,
+            '0: '0
+        };
+
+        reset = 1;
+        start = 0;
+        repeat (2) @(posedge clk);
+        reset = 0;
+        @(posedge clk);
+        foreach (test_cases[key]) begin
+            wait (ready);
+            num = key;
+            @(posedge clk);
+            start = 1;
+            @(posedge clk);
+            start = 0;
+            @(posedge clk);
+            wait(ready);
+            assert (crc === test_cases[key])
+                else $error("Invalid crc, found 0x%x but expected 0x%x",crc,test_cases[key]);
+        end
+
+        $finish;
+
+    end
+
+endmodule
@@ -0,0 +1,81 @@
+module read_command_tb;
+    bit clk;
+    logic reset;
+    logic listen;
+    logic [2:0] response_type;
+    logic sd_cmd;
+    wire received;
+    wire [135:0] out_data;
+
+
+    read_command dut (.*);
+
+    initial forever #10 clk = ~clk;
+
+
+    initial begin
+        $display("Testing read_command module");
+        sd_cmd = 1;
+        response_type = 0;
+        reset = 1;
+        listen = 0;
+        repeat (2) @(posedge clk);
+
+        reset = 0;
+        listen = 1;
+        response_type = 2;
+        @(posedge clk);
+        listen = 0;
+        response_type = 0;
+        repeat (5) @(posedge clk);
+        send_byte('h01);
+        for (int i=0; i<15; i++)
+            send_byte('hAA);
+        send_byte('h01);
+        @(posedge clk);
+        // NOTE: the received signal takes an extra cycle to propogate because
+        // it is loaded into a register
+        @(posedge clk);
+        #1;
+        assert (received === 1)
+            else $error("received signal not high");
+        assert (out_data === 'h01AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA01)
+            else $error("out_dat incorrect, found 0x%x but expected 0x01AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA01",out_data);
+        
+
+        repeat (7) @(posedge clk);
+
+        listen = 1;
+        response_type = 3;
+        @(posedge clk);
+        listen = 0;
+        response_type = 0;
+        send_byte('h00);
+        send_byte('hAB);
+        send_byte('hCD);
+        send_byte('hEF);
+        send_byte('h12);
+        send_byte('h01);
+        // Return sd_cmd to inactive state
+        @(posedge clk) sd_cmd = 1;
+
+        @(posedge clk);
+        #1;
+        assert (received === 1)
+            else $error("received signal not high");
+        assert (out_data === 136'h00ABCDEF1201)
+            else $error("out_dat incorrect, found %b but expected 0x00ABCDEF1201",out_data);
+        
+
+        @(posedge clk);
+        $finish;
+    end
+
+    task automatic send_byte(logic [7:0] b);
+        for (int i = 8; i != 0; i--) begin
+            @(posedge clk) sd_cmd = b[i-1];
+        end
+    endtask
+
+
+endmodule
@@ -0,0 +1,140 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+import sdvd_defs::SPEED;
+
+module read_data_tb;
+    logic clk, sd_clk, reset;
+
+    // Control signals
+    logic play, stop;
+    SPEED speed;
+
+    // Whether the audio buffer is currently playing
+    logic playing;
+
+    // A 16-bit audio sample to output
+    logic [15:0] sample;
+
+    logic sd_data;
+
+    audio_buffer_interface bufferInterface(); 
+
+    logic [10:0] counter;
+
+    logic [15:0] test_memory [1023:0];
+    audio_buffer audioDut(.driver(bufferInterface.receiver), .*);
+    read_data readerDut(sd_clk,reset,sd_data,bufferInterface.driver);
+
+    // The writer's clock should be much faster than the 48khz buffer clock
+    initial sd_clk = 0;
+    always #5 sd_clk = ~sd_clk;
+
+
+    // An order of magnitude difference is fine
+    initial clk = 0;
+    always #500 clk = ~clk;
+
+    // Reader
+    initial begin
+        `ifdef DEBUG
+        $monitor("PLAYING: %b ADDR: 0x%x DATA: 0x%x WILLDELAY: %b",
+                 playing, dut.address, dut.doutb,dut.delay);
+        `endif
+        fork
+        //Reader
+        begin
+            play = 0;
+            stop = 0;
+            clk = 0;
+            reset = 0;
+            speed = 1;
+            @(posedge clk)
+            reset = 1;
+            @(posedge clk)
+            reset = 0;
+            play = 1;
+            @(posedge clk)
+            assert (playing == 1) else $error("Audio buffer not playing");
+            // Wait an extra clock cycle because of the blockmem delay
+            @(posedge clk)
+            // The most basic test we can do here is an incrementing counter,
+            // where the stored sample is the same as the address
+            $display("Running linear test");
+            for (counter = 0; counter < 1024; counter++) begin
+                #1
+                assert ({5'b0, counter} === sample) else
+                    $error("Invalid sample, expected 0x%x but found 0x%x",counter,sample);
+                @(posedge clk);
+            end
+            $display("Running randomized test");
+            counter = 0;
+            while(counter < 1024) begin
+                #1
+                assert (test_memory[counter[9:0]] === sample) else
+                    $error("Invalid sample, expected 0x%x but found 0x%x at location 0x%x",test_memory[counter[9:0]],sample,counter);
+                @(posedge clk);
+                counter++;
+            end
+
+        end
+        // Writer
+        begin
+            for (int i=0; i<1024; i++)
+                test_memory[i]=$urandom;
+            // Wait til buffer is done resetting
+            @(posedge clk);
+            @(posedge clk);
+            // linear test
+            write_linear_sd(0);
+            write_linear_sd(256);
+            write_linear_sd(512);
+            write_linear_sd(256*3);
+            wait (bufferInterface.address_half==1);
+            // random test, write to lower half of memory
+            write_random_sd(0);
+            write_random_sd(256);
+            wait (bufferInterface.address_half==0);
+            // random test, write to upper half of memory
+            write_random_sd(512);
+            write_random_sd(256*3);
+        end
+        join
+        $finish;
+    end
+    task automatic write_random_sd(int start);
+        @(posedge sd_clk);
+        sd_data = 1;
+        // send start bit
+        @(posedge sd_clk);
+        // send 256 data bits
+        sd_data = 0;
+        for (int i = 0; i < 256; i++) begin
+            write_byte(test_memory[start+i][7:0]);
+            write_byte(test_memory[start+i][15:8]);
+        end
+        // Simulate randomized crc bits and stop bit
+        repeat (16) @(posedge sd_clk) sd_data=$urandom;
+        @(posedge sd_clk) sd_data=1;
+    endtask
+    task automatic write_linear_sd(int start);
+        @(posedge sd_clk);
+        sd_data = 1;
+        // send start bit
+        @(posedge sd_clk);
+        // send 256 data bits
+        sd_data = 0;
+        for (int i = 0; i < 256; i++) begin
+            write_byte(start[7:0]);
+            write_byte(start[15:8]);
+            start = start+1;
+        end
+        // Simulate crc bits and stop bit
+        repeat (17) @(posedge sd_clk) sd_data=1;
+    endtask
+    task automatic write_byte(logic [7:0] b);
+        for (int i=0; i<8; i++)
+            @(posedge sd_clk) sd_data=b[7-i];
+    endtask
+
+endmodule
@@ -0,0 +1,155 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+
+module rom_sd_tb;
+    bit clk,reset;
+    wire ready;
+    int errors;
+    logic [10:0] i;
+
+    audio_buffer_interface buffer();
+
+    rom_sd #("consecutive.mem") dut (clk,reset,ready,buffer.driver);
+
+
+    initial forever #10 clk = ~clk;
+
+    initial begin
+        reset = 1;
+        buffer.address_half = 0;
+        @(posedge clk);
+        reset = 0;
+        // Audio data should not be flowing yet
+        #1 assert (buffer.dina == 0) 
+        else begin
+            errors++;
+            $error("Data not zero after reset, found 0x%x",buffer.dina);
+        end
+        repeat (3) @(posedge clk);
+        for (i = 0; i < 1024;) begin
+            @(posedge clk);
+            #1
+
+            assert (buffer.addra === i)
+            else begin 
+                errors++;
+                $error("Incorrect address, expected %x found %x",i,buffer.addra);
+            end
+
+            assert (buffer.dina === ((i + 1) % 256))
+            else begin 
+                errors++;
+                $error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
+            end
+
+            assert (i == 0 || buffer.ena === 1)
+            else begin 
+                $error("Enable not high");
+                errors++;
+            end
+
+            assert (buffer.address_half == 0)
+            else begin 
+                errors++;
+                $error("Incorrect address half, expected 0 but found %d",buffer.address_half);
+            end
+
+            i = i + 1;
+        end
+        // Wait a cycle for the buffer to catch up
+        @(posedge clk);
+        // Make sure that we start waiting and that we signal that the buffer
+        // is ready
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after first full cycle");
+        end
+        assert(ready === 1)
+        else begin
+            errors++;
+            $error("Buffer did not signal ready");
+        end
+
+        assert(dut.buffer_half === 1)
+        else begin
+            errors++;
+            $error("Buffer half did not correctly change to 1");
+        end
+
+        // Set the address half high so we can test waiting/catching up to the
+        // buffer
+        buffer.address_half = 1;
+        repeat (100) @(posedge clk);
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after first full cycle");
+        end
+
+        buffer.address_half = 0;
+        repeat (3) @(posedge clk);
+        // Check that sending into the upper half of the buffer works as
+        // expected
+        while (i != 0) begin
+            @(posedge clk);
+            #1
+
+            assert (buffer.addra === i)
+            else begin 
+                errors++;
+                $error("Incorrect address, expected %x found %x",i,buffer.addra);
+            end
+
+            assert (buffer.dina === ((i + 1) % 256))
+            else begin 
+                errors++;
+                $error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
+            end
+
+            assert (i == 0 || buffer.ena === 1)
+            else begin 
+                $error("Enable not high");
+                errors++;
+            end
+
+            assert (buffer.address_half == 0)
+            else begin 
+                errors++;
+                $error("Incorrect address half, expected 0 but found %d",buffer.address_half);
+            end
+
+            i = i + 1;
+        end
+
+        // Wait a cycle for the buffer to catch up
+        @(posedge clk);
+        // Make sure that we start waiting
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after second full cycle");
+        end
+        assert(ready === 1)
+        else begin
+            errors++;
+            $error("Buffer did not signal ready");
+        end
+
+        assert(dut.buffer_half === 0)
+        else begin
+            errors++;
+            $error("Buffer half did not correctly change to 0");
+        end
+
+
+        $display("Found %0d errors while testing rom_sd",errors);
+
+        $finish;
+
+
+
+    end
+
+endmodule
@@ -0,0 +1,45 @@
+module sd_controller_tb;
+    bit slow_clk,fast_clk,crc_clk;
+    logic reset,sd_data;
+    wire sd_cmd;
+    wire ready;
+    wire clk;
+    audio_buffer_interface buffer ();
+
+    sd_controller dut (.buffer(buffer.driver), .*);
+
+    bit sd_write;
+
+    assign sd_cmd = sd_write ? 'z : 0;
+
+    initial forever #100 slow_clk = ~slow_clk;
+
+    initial forever #1 crc_clk = ~crc_clk;
+    initial forever #10 fast_clk = ~fast_clk;
+
+    initial begin
+
+        sd_write = 1;
+        reset = 1;
+        repeat (2) @(posedge slow_clk);
+        reset = 0;
+        repeat (200) @(posedge slow_clk);
+        send_response();
+
+        repeat (100) @(posedge slow_clk);
+        send_response();
+        repeat (100) @(posedge slow_clk);
+
+        $finish;
+
+    end
+
+    task automatic send_response();
+        for(int i=0;i<47;i++)
+            @(posedge slow_clk) sd_write = 0;
+        @(posedge slow_clk) sd_write = 1;
+    endtask
+
+
+
+endmodule
@@ -0,0 +1,63 @@
+module send_command_tb;
+
+bit clk;
+// The crc should be clocked way faster than the sender
+bit crc_clk;
+logic reset;
+logic start;
+logic [5:0] command;
+logic [31:0] arguments;
+wire ready;
+wire sd_cmd;
+
+logic [47:0] fill_me;
+int counter;
+
+logic sd_cmd_real;
+
+assign sd_cmd_real = (sd_cmd === 'z) ? 1 : 0;
+
+send_command dut(.*);
+
+initial forever #100 clk = ~clk;
+initial forever #20 crc_clk = ~crc_clk;
+
+
+
+initial begin
+    reset = 1;
+    start = 0;
+
+    repeat (2) @(posedge clk);
+
+    reset = 0;
+    @(posedge clk);
+
+    start = 1;
+    command = 8;
+    arguments = 'h1AA;
+
+    counter = 48;
+
+    @(posedge clk);
+
+    // Try receiving the CMD8
+    while (counter != 0) begin
+        // Check for the start bit, or that we're receiving a message
+        if (sd_cmd_real != 1 || counter != 48) begin
+            fill_me = {fill_me[46:0], sd_cmd_real};
+            counter--;
+        end
+        @(posedge clk);
+    end
+
+    assert (fill_me === {2'b01, 6'd8, 32'h1AA, 8'h87})
+        else $error("Received wrong command, got 0x%x",fill_me);
+
+    assert (ready)
+        else $error("SD command sender not ready");
+
+
+    $finish;
+end
+endmodule
@@ -1,3 +1,11 @@
+/****
+ * seconds_display_tb.sv - testbench for the seconds_display module.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * */
+
 `timescale 1ns / 1ps
 module seconds_display_tb;
 int errors = 0;
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="crc_gen_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="crc_gen_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="609.789 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,276.290 ns"></ZoomEndTime>
+      <Cursor1Time time="209.703 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="533"></NameColumnWidth>
+      <ValueColumnWidth column_width="219"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="10" />
+   <wvobject type="logic" fp_name="/crc_gen_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/crc_gen_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/crc_gen_tb/start">
+      <obj_property name="ElementShortName">start</obj_property>
+      <obj_property name="ObjectShortName">start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/crc_gen_tb/ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/num">
+      <obj_property name="ElementShortName">num[39:0]</obj_property>
+      <obj_property name="ObjectShortName">num[39:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/crc">
+      <obj_property name="ElementShortName">crc[6:0]</obj_property>
+      <obj_property name="ObjectShortName">crc[6:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/CRCBITS">
+      <obj_property name="ElementShortName">CRCBITS[31:0]</obj_property>
+      <obj_property name="ObjectShortName">CRCBITS[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/COMMANDLEN">
+      <obj_property name="ElementShortName">COMMANDLEN[31:0]</obj_property>
+      <obj_property name="ObjectShortName">COMMANDLEN[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/POLYNOMIAL">
+      <obj_property name="ElementShortName">POLYNOMIAL[31:0]</obj_property>
+      <obj_property name="ObjectShortName">POLYNOMIAL[31:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/crc_gen_tb/dut/counter">
+      <obj_property name="ElementShortName">counter[6:0]</obj_property>
+      <obj_property name="ObjectShortName">counter[6:0]</obj_property>
+   </wvobject>
+</wave_config>
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="read_command_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="read_command_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,370.001 ns"></ZoomEndTime>
+      <Cursor1Time time="330.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="533"></NameColumnWidth>
+      <ValueColumnWidth column_width="187"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="11" />
+   <wvobject type="logic" fp_name="/read_command_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_command_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_command_tb/listen">
+      <obj_property name="ElementShortName">listen</obj_property>
+      <obj_property name="ObjectShortName">listen</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_command_tb/sd_cmd">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_command_tb/received">
+      <obj_property name="ElementShortName">received</obj_property>
+      <obj_property name="ObjectShortName">received</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/out_data">
+      <obj_property name="ElementShortName">out_data[39:0]</obj_property>
+      <obj_property name="ObjectShortName">out_data[39:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/dut/state">
+      <obj_property name="ElementShortName">state[2:0]</obj_property>
+      <obj_property name="ObjectShortName">state[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/dut/counter">
+      <obj_property name="ElementShortName">counter[6:0]</obj_property>
+      <obj_property name="ObjectShortName">counter[6:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/dut/data_reg">
+      <obj_property name="ElementShortName">data_reg[39:0]</obj_property>
+      <obj_property name="ObjectShortName">data_reg[39:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/response_type">
+      <obj_property name="ElementShortName">response_type[2:0]</obj_property>
+      <obj_property name="ObjectShortName">response_type[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_command_tb/dut/response_type_reg">
+      <obj_property name="ElementShortName">response_type_reg[2:0]</obj_property>
+      <obj_property name="ObjectShortName">response_type_reg[2:0]</obj_property>
+   </wvobject>
+</wave_config>
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="read_data_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="read_data_tb" />
+            <top_module name="sdvd_defs" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="1,438.800 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,718.201 ns"></ZoomEndTime>
+      <Cursor1Time time="618.800 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="533"></NameColumnWidth>
+      <ValueColumnWidth column_width="155"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="18" />
+   <wvobject type="logic" fp_name="/read_data_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/sd_clk">
+      <obj_property name="ElementShortName">sd_clk</obj_property>
+      <obj_property name="ObjectShortName">sd_clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/play">
+      <obj_property name="ElementShortName">play</obj_property>
+      <obj_property name="ObjectShortName">play</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/stop">
+      <obj_property name="ElementShortName">stop</obj_property>
+      <obj_property name="ObjectShortName">stop</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/speed">
+      <obj_property name="ElementShortName">speed[3:0]</obj_property>
+      <obj_property name="ObjectShortName">speed[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/playing">
+      <obj_property name="ElementShortName">playing</obj_property>
+      <obj_property name="ObjectShortName">playing</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/sample">
+      <obj_property name="ElementShortName">sample[15:0]</obj_property>
+      <obj_property name="ObjectShortName">sample[15:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/counter">
+      <obj_property name="ElementShortName">counter[10:0]</obj_property>
+      <obj_property name="ObjectShortName">counter[10:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/test_memory">
+      <obj_property name="ElementShortName">test_memory[1023:0][15:0]</obj_property>
+      <obj_property name="ObjectShortName">test_memory[1023:0][15:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/bufferInterface/driver/addra">
+      <obj_property name="ElementShortName">addra[10:0]</obj_property>
+      <obj_property name="ObjectShortName">addra[10:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/bufferInterface/driver/dina">
+      <obj_property name="ElementShortName">dina[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dina[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/bufferInterface/driver/ena">
+      <obj_property name="ElementShortName">ena</obj_property>
+      <obj_property name="ObjectShortName">ena</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/bufferInterface/driver/address_half">
+      <obj_property name="ElementShortName">address_half</obj_property>
+      <obj_property name="ObjectShortName">address_half</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/read_data_tb/sd_data">
+      <obj_property name="ElementShortName">sd_data</obj_property>
+      <obj_property name="ObjectShortName">sd_data</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/readerDut/byte_shift">
+      <obj_property name="ElementShortName">byte_shift[7:0]</obj_property>
+      <obj_property name="ObjectShortName">byte_shift[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/readerDut/byte_counter">
+      <obj_property name="ElementShortName">byte_counter[3:0]</obj_property>
+      <obj_property name="ObjectShortName">byte_counter[3:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/read_data_tb/readerDut/counter">
+      <obj_property name="ElementShortName">counter[13:0]</obj_property>
+      <obj_property name="ObjectShortName">counter[13:0]</obj_property>
+   </wvobject>
+</wave_config>
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="rom_sd_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="rom_sd_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+      <ZoomEndTime time="143.201 ns"></ZoomEndTime>
+      <Cursor1Time time="0.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="453"></NameColumnWidth>
+      <ValueColumnWidth column_width="200"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="10" />
+   <wvobject type="logic" fp_name="/rom_sd_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/rom_data">
+      <obj_property name="ElementShortName">rom_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rom_data[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/current">
+      <obj_property name="ElementShortName">current[2:0]</obj_property>
+      <obj_property name="ObjectShortName">current[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/rom_addr">
+      <obj_property name="ElementShortName">rom_addr[16:0]</obj_property>
+      <obj_property name="ObjectShortName">rom_addr[16:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/dut/rom_enable">
+      <obj_property name="ElementShortName">rom_enable</obj_property>
+      <obj_property name="ObjectShortName">rom_enable</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/buffer/addra">
+      <obj_property name="ElementShortName">addra[10:0]</obj_property>
+      <obj_property name="ObjectShortName">addra[10:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/buffer/dina">
+      <obj_property name="ElementShortName">dina[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dina[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/buffer/ena">
+      <obj_property name="ElementShortName">ena</obj_property>
+      <obj_property name="ObjectShortName">ena</obj_property>
+   </wvobject>
+</wave_config>
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="sd_controller_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="sd_controller_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="41,685.336 ns"></ZoomStartTime>
+      <ZoomEndTime time="44,957.696 ns"></ZoomEndTime>
+      <Cursor1Time time="0.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="469"></NameColumnWidth>
+      <ValueColumnWidth column_width="172"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="11" />
+   <wvobject type="logic" fp_name="/sd_controller_tb/slow_clk">
+      <obj_property name="ElementShortName">slow_clk</obj_property>
+      <obj_property name="ObjectShortName">slow_clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/fast_clk">
+      <obj_property name="ElementShortName">fast_clk</obj_property>
+      <obj_property name="ObjectShortName">fast_clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/crc_clk">
+      <obj_property name="ElementShortName">crc_clk</obj_property>
+      <obj_property name="ObjectShortName">crc_clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/sd_data">
+      <obj_property name="ElementShortName">sd_data</obj_property>
+      <obj_property name="ObjectShortName">sd_data</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/sd_cmd">
+      <obj_property name="ElementShortName">sd_cmd</obj_property>
+      <obj_property name="ObjectShortName">sd_cmd</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/sd_controller_tb/dut/state">
+      <obj_property name="ElementShortName">state[5:0]</obj_property>
+      <obj_property name="ObjectShortName">state[5:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/dut/sender/ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/sd_controller_tb/dut/reader/received">
+      <obj_property name="ElementShortName">received</obj_property>
+      <obj_property name="ObjectShortName">received</obj_property>
+   </wvobject>
+</wave_config>
Author	SHA1	Message	Date
Dilanthi	9af830daa0	comment clean up	2025-06-10 02:51:18 -07:00
Dilanthi	53b48c0bce	comment clean up for segment_display folder	2025-06-10 01:38:52 -07:00
Dilanthi	a07e811a16	code clean up for playback_controller.sv	2025-06-10 01:30:51 -07:00
uelen	fe227d1b61	Broken SD card ci/woodpecker/push/test-workflow Pipeline was successful Details How tf did it break bro	2025-06-09 15:41:13 -07:00
uelen	71eecd18e8	Added modules to read sdcard data and cmd response ci/woodpecker/push/test-workflow Pipeline was successful Details These were realy headaches but the testbenches are passing. We need to take a look at the audio_buffer testbench for sure, it is way wrong and needs reworked to use the interface. Should do a pass through every module probably.	2025-06-07 21:57:17 -07:00
uelen	e32563131f	Added command signal driver module ci/woodpecker/push/test-workflow Pipeline was successful Details	2025-06-06 20:49:18 -07:00
uelen	71f08bdf15	Add CRC generation for sd card ci/woodpecker/push/test-workflow Pipeline was successful Details Works great according to the testbench	2025-06-06 18:13:14 -07:00
uelen	35cb264b26	Its working! Demo commit ci/woodpecker/push/test-workflow Pipeline was successful Details We have something at least, audio is working and sounding dang good	2025-06-06 01:06:20 -07:00
uelen	7980424dc8	Lots of changes, trying to get ROM working ci/woodpecker/push/test-workflow Pipeline was successful Details I think I did some funny math errors so new goal is 8-bit pcm	2025-06-05 18:48:53 -07:00
Dilanthi	02e2d77640	header for rom_sd.sv ci/woodpecker/push/test-workflow Pipeline was successful Details	2025-06-04 14:34:49 -07:00
Dilanthi	1beb6cbf5c	Implement rom_sd state machine ci/woodpecker/push/test-workflow Pipeline was successful Details	2025-06-04 13:17:36 -07:00
uelen	89558d8313	More fixup on rom_sd ci/woodpecker/push/test-workflow Pipeline was successful Details	2025-06-03 22:36:57 -07:00
uelen	2387fdbe3b	Fixup on rom_sd flowchart ci/woodpecker/push/test-workflow Pipeline was successful Details	2025-06-03 22:36:01 -07:00
uelen	0015a0d7bc	Merge pull request 'added headers/ updated old ones' (#3 ) from header_changes into master ci/woodpecker/push/test-workflow Pipeline was successful Details Reviewed-on: #3	2025-06-03 00:51:19 +00:00
uelen	b9b6be7cbe	Typo fixup	2025-06-02 17:47:35 -07:00
Dilanthi	636b375c48	added headers/ updated old ones	2025-06-02 17:36:27 -07:00
Dilanthi	d4d9d604b9	Merge pull request 'Initial work on rom_sd' (#2 ) from add_more_docs into master ci/woodpecker/push/test-workflow Pipeline was successful Details Reviewed-on: #2	2025-06-02 21:24:45 +00:00
Dilanthi	aa8ffb8213	Merge pull request 'Fixed up debouncer and added some assertions' (#1 ) from debouncer_fixup into master ci/woodpecker/push/test-workflow Pipeline was successful Details Reviewed-on: #1	2025-06-02 21:23:34 +00:00
uelen	dff929de84	Initial work on rom_sd This module needs way reworked to just be a state machine. I was trying to get way too tricky with it so I went back to the drawing board and made a state machine diagram for it. The diagram is included with this commit. I also moved the current collection of documentation to a doc/ folder, and added a second-long audio rom to test everything out once the rom_sd is working.	2025-06-02 14:02:50 -07:00