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Add CRC generation for sd card
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Works great according to the testbench
This commit is contained in:
Waylon Cude 2025-06-06 18:13:14 -07:00
parent 35cb264b26
commit 71f08bdf15
5 changed files with 222 additions and 2 deletions
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57
SDVD.xpr
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@ -45,7 +45,7 @@
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="rom_sd_tb"/>
<Option Name="ActiveSimSet" Val="crc_gen_tb"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
@ -61,7 +61,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="nexys-a7-100t"/>
<Option Name="WTXSimLaunchSim" Val="133"/>
<Option Name="WTXSimLaunchSim" Val="138"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -202,6 +202,20 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/design/sd/send_command.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/design/sd/crc_gen.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="nexys_a7_top"/>
@ -430,6 +444,45 @@
<Option Name="xsim.simulate.runtime" Val="1s"/>
</Config>
</FileSet>
<FileSet Name="crc_gen_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/crc_gen_tb" RelGenDir="$PGENDIR/crc_gen_tb">
<File Path="$PPRDIR/verification/sd/rom_sd_tb.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/verification/sd/crc_gen_tb.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/verification/waveform_configs/crc_gen_tb_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="crc_gen_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/crc_gen_tb_behav.wcfg"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
<Option Name="xsim.simulate.runtime" Val="1s"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">

41
design/sd/crc_gen.sv Normal file
View File

@ -0,0 +1,41 @@
// parameterizable sequential crc generator
// This probably could be combinational logic too, though it would be way slow
module crc_gen #(
parameter CRCBITS=7,
parameter COMMANDLEN=40,
parameter POLYNOMIAL='h89
) (
input clk,
input reset,
input start,
input [COMMANDLEN-1:0] num,
output logic ready,
output logic [CRCBITS-1:0] crc
);
logic [$clog2(COMMANDLEN):0] counter;
logic [COMMANDLEN+CRCBITS-1:0] div_reg;
always_ff @(posedge clk) begin
if (reset) begin
counter <= 0;
crc <= 0;
end
else if (start) begin
counter <= COMMANDLEN;
div_reg <= {num, {CRCBITS{1'b0}}};
ready <= 0;
end
else if (counter != 0) begin
if (div_reg[counter+CRCBITS-1] == 1) begin
div_reg <= div_reg ^ (POLYNOMIAL << (counter-1));
end
counter <= counter - 1;
end
else begin
ready <= 1;
crc <= div_reg[CRCBITS-1:0];
end
end
endmodule

14
design/sd/send_command.sv Normal file
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@ -0,0 +1,14 @@
module send_command(
input clk,
input reset,
input start,
input [5:0] command,
input [31:0] arguments
);
// Some commands have hardcoded crcs, and as such they can be found in a LUT,
// otherwise we need to shell out to the crc module and wait a while for it to
// run
endmodule

49
verification/sd/crc_gen_tb.sv Normal file
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@ -0,0 +1,49 @@
module crc_gen_tb;
parameter CRCBITS=7;
parameter COMMANDLEN=40;
parameter POLYNOMIAL='h89;
logic clk, reset, start, ready;
logic [COMMANDLEN-1:0] num;
logic [CRCBITS-1:0] crc;
logic [CRCBITS-1:0] test_cases [logic [COMMANDLEN-1:0]];
crc_gen #(CRCBITS,COMMANDLEN,POLYNOMIAL) dut (.*);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
test_cases = '{
'h1234567890: 'h10,
'hBEEFB05535: 'h05,
'h5544992211: 'h17,
'0: '0
};
reset = 1;
start = 0;
repeat (2) @(posedge clk);
reset = 0;
@(posedge clk);
foreach (test_cases[key]) begin
wait (ready);
num = key;
@(posedge clk);
start = 1;
@(posedge clk);
start = 0;
@(posedge clk);
wait(ready);
assert (crc === test_cases[key])
else $error("Invalid crc, found 0x%x but expected 0x%x",crc,test_cases[key]);
end
$finish;
end
endmodule

63
verification/waveform_configs/crc_gen_tb_behav.wcfg Normal file
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@ -0,0 +1,63 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="crc_gen_tb_behav.wdb" id="1">
<top_modules>
<top_module name="crc_gen_tb" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="609.789 ns"></ZoomStartTime>
<ZoomEndTime time="1,276.290 ns"></ZoomEndTime>
<Cursor1Time time="209.703 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="533"></NameColumnWidth>
<ValueColumnWidth column_width="219"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="10" />
<wvobject type="logic" fp_name="/crc_gen_tb/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/crc_gen_tb/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/crc_gen_tb/start">
<obj_property name="ElementShortName">start</obj_property>
<obj_property name="ObjectShortName">start</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/crc_gen_tb/ready">
<obj_property name="ElementShortName">ready</obj_property>
<obj_property name="ObjectShortName">ready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/num">
<obj_property name="ElementShortName">num[39:0]</obj_property>
<obj_property name="ObjectShortName">num[39:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/crc">
<obj_property name="ElementShortName">crc[6:0]</obj_property>
<obj_property name="ObjectShortName">crc[6:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/CRCBITS">
<obj_property name="ElementShortName">CRCBITS[31:0]</obj_property>
<obj_property name="ObjectShortName">CRCBITS[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/COMMANDLEN">
<obj_property name="ElementShortName">COMMANDLEN[31:0]</obj_property>
<obj_property name="ObjectShortName">COMMANDLEN[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/POLYNOMIAL">
<obj_property name="ElementShortName">POLYNOMIAL[31:0]</obj_property>
<obj_property name="ObjectShortName">POLYNOMIAL[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/crc_gen_tb/dut/counter">
<obj_property name="ElementShortName">counter[6:0]</obj_property>
<obj_property name="ObjectShortName">counter[6:0]</obj_property>
</wvobject>
</wave_config>