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Works great according to the testbench
15 lines
303 B
Systemverilog
15 lines
303 B
Systemverilog
module send_command(
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input clk,
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input reset,
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input start,
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input [5:0] command,
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input [31:0] arguments
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);
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// Some commands have hardcoded crcs, and as such they can be found in a LUT,
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// otherwise we need to shell out to the crc module and wait a while for it to
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// run
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endmodule
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