How tf did it break bro
This commit is contained in:
parent
71eecd18e8
commit
fe227d1b61
2
.gitignore
vendored
2
.gitignore
vendored
@ -2,4 +2,6 @@
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*.log
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xsim.dir
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SDVD.*
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.Xil/
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vivado_pid*
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!SDVD.xpr
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@ -153,14 +153,14 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports BTNR]
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#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
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##Micro SD Connector
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#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
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#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
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#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
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#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
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#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
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#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
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#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
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#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports SD_RESET]
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set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports SD_CD]
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set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports SD_SCK]
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set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports SD_CMD]
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set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[0]}]
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[1]}]
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set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[2]}]
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set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {SD_DAT[3]}]
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##Accelerometer
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#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
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@ -217,137 +217,127 @@ set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports AUD_SD]
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#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[4]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[0]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[1]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[2]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[3]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[5]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[6]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/pulse_counter_reg[7]}]
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set_property MARK_DEBUG true [get_nets audioOutput/AUD_PWM_TRI]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[3]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[4]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[5]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[0]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[2]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[6]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[7]}]
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set_property MARK_DEBUG true [get_nets {audioOutput/D[1]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[5]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[6]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[7]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[0]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[1]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[2]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[3]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/rom_data[4]}]
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set_property MARK_DEBUG true [get_nets romSdPlayer/rom_addr]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[5]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[0]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[1]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[2]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[3]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[4]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[6]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[7]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[8]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[9]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/audio_interface\\.addra[10]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[17]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[5]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[1]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[2]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[12]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[14]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[13]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[15]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[3]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[4]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[6]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[7]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[18]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[16]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[8]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[9]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[10]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/in7[11]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[10]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[0]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[1]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[2]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[3]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[5]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[6]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[13]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[7]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[8]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[9]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[14]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[11]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[12]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[15]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[4]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[16]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[17]}]
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set_property MARK_DEBUG true [get_nets {romSdPlayer/xpm_memory_sprom_inst/addra[18]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[0]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[4]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[3]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[8]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[1]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[2]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[9]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[5]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[6]}]
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set_property MARK_DEBUG true [get_nets {audioBuffer/buffer/addrb[7]}]
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set_property MARK_DEBUG true [get_nets audioClock_n_0]
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connect_debug_port u_ila_0/probe2 [get_nets [list {realSdPlayer/address[0]} {realSdPlayer/address[1]} {realSdPlayer/address[2]} {realSdPlayer/address[3]} {realSdPlayer/address[4]} {realSdPlayer/address[5]} {realSdPlayer/address[6]} {realSdPlayer/address[7]} {realSdPlayer/address[8]} {realSdPlayer/address[9]} {realSdPlayer/address[10]} {realSdPlayer/address[11]} {realSdPlayer/address[12]} {realSdPlayer/address[13]} {realSdPlayer/address[14]} {realSdPlayer/address[15]} {realSdPlayer/address[16]} {realSdPlayer/address[17]} {realSdPlayer/address[18]} {realSdPlayer/address[19]} {realSdPlayer/address[20]} {realSdPlayer/address[21]} {realSdPlayer/address[22]} {realSdPlayer/address[23]} {realSdPlayer/address[24]} {realSdPlayer/address[25]} {realSdPlayer/address[26]} {realSdPlayer/address[27]} {realSdPlayer/address[28]} {realSdPlayer/address[29]} {realSdPlayer/address[30]} {realSdPlayer/address[31]}]]
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set_property MARK_DEBUG true [get_nets reset]
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connect_debug_port u_ila_0/probe4 [get_nets [list {realSdPlayer/reader/next_state[0]} {realSdPlayer/reader/next_state[1]} {realSdPlayer/reader/next_state[2]}]]
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connect_debug_port u_ila_0/probe7 [get_nets [list {realSdPlayer/reader/state[0]} {realSdPlayer/reader/state[1]} {realSdPlayer/reader/state[2]}]]
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connect_debug_port u_ila_0/probe6 [get_nets [list {realSdPlayer/sender/to_send[0]} {realSdPlayer/sender/to_send[1]} {realSdPlayer/sender/to_send[2]} {realSdPlayer/sender/to_send[3]} {realSdPlayer/sender/to_send[4]} {realSdPlayer/sender/to_send[5]} {realSdPlayer/sender/to_send[6]} {realSdPlayer/sender/to_send[7]} {realSdPlayer/sender/to_send[8]} {realSdPlayer/sender/to_send[9]} {realSdPlayer/sender/to_send[10]} {realSdPlayer/sender/to_send[11]} {realSdPlayer/sender/to_send[12]} {realSdPlayer/sender/to_send[13]} {realSdPlayer/sender/to_send[14]} {realSdPlayer/sender/to_send[15]} {realSdPlayer/sender/to_send[16]} {realSdPlayer/sender/to_send[17]} {realSdPlayer/sender/to_send[18]} {realSdPlayer/sender/to_send[19]} {realSdPlayer/sender/to_send[20]} {realSdPlayer/sender/to_send[21]} {realSdPlayer/sender/to_send[22]} {realSdPlayer/sender/to_send[23]} {realSdPlayer/sender/to_send[24]} {realSdPlayer/sender/to_send[25]} {realSdPlayer/sender/to_send[26]} {realSdPlayer/sender/to_send[27]} {realSdPlayer/sender/to_send[28]} {realSdPlayer/sender/to_send[29]} {realSdPlayer/sender/to_send[30]} {realSdPlayer/sender/to_send[31]} {realSdPlayer/sender/to_send[32]} {realSdPlayer/sender/to_send[33]} {realSdPlayer/sender/to_send[34]} {realSdPlayer/sender/to_send[35]} {realSdPlayer/sender/to_send[36]} {realSdPlayer/sender/to_send[37]} {realSdPlayer/sender/to_send[38]} {realSdPlayer/sender/to_send[39]} {realSdPlayer/sender/to_send[40]} {realSdPlayer/sender/to_send[41]} {realSdPlayer/sender/to_send[42]} {realSdPlayer/sender/to_send[43]} {realSdPlayer/sender/to_send[44]} {realSdPlayer/sender/to_send[45]} {realSdPlayer/sender/to_send[46]} {realSdPlayer/sender/to_send[47]}]]
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set_property MARK_DEBUG true [get_nets realSdPlayer/fast_clk]
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connect_debug_port u_ila_0/probe8 [get_nets [list {realSdPlayer/fastSender/to_send[0]} {realSdPlayer/fastSender/to_send[1]} {realSdPlayer/fastSender/to_send[2]} {realSdPlayer/fastSender/to_send[3]} {realSdPlayer/fastSender/to_send[4]} {realSdPlayer/fastSender/to_send[5]} {realSdPlayer/fastSender/to_send[6]} {realSdPlayer/fastSender/to_send[7]} {realSdPlayer/fastSender/to_send[8]} {realSdPlayer/fastSender/to_send[9]} {realSdPlayer/fastSender/to_send[10]} {realSdPlayer/fastSender/to_send[11]} {realSdPlayer/fastSender/to_send[12]} {realSdPlayer/fastSender/to_send[13]} {realSdPlayer/fastSender/to_send[14]} {realSdPlayer/fastSender/to_send[15]} {realSdPlayer/fastSender/to_send[16]} {realSdPlayer/fastSender/to_send[17]} {realSdPlayer/fastSender/to_send[18]} {realSdPlayer/fastSender/to_send[19]} {realSdPlayer/fastSender/to_send[20]} {realSdPlayer/fastSender/to_send[21]} {realSdPlayer/fastSender/to_send[22]} {realSdPlayer/fastSender/to_send[23]} {realSdPlayer/fastSender/to_send[24]} {realSdPlayer/fastSender/to_send[25]} {realSdPlayer/fastSender/to_send[26]} {realSdPlayer/fastSender/to_send[27]} {realSdPlayer/fastSender/to_send[28]} {realSdPlayer/fastSender/to_send[29]} {realSdPlayer/fastSender/to_send[30]} {realSdPlayer/fastSender/to_send[31]} {realSdPlayer/fastSender/to_send[32]} {realSdPlayer/fastSender/to_send[33]} {realSdPlayer/fastSender/to_send[34]} {realSdPlayer/fastSender/to_send[35]} {realSdPlayer/fastSender/to_send[36]} {realSdPlayer/fastSender/to_send[37]} {realSdPlayer/fastSender/to_send[38]} {realSdPlayer/fastSender/to_send[39]} {realSdPlayer/fastSender/to_send[40]} {realSdPlayer/fastSender/to_send[41]} {realSdPlayer/fastSender/to_send[42]} {realSdPlayer/fastSender/to_send[43]} {realSdPlayer/fastSender/to_send[44]} {realSdPlayer/fastSender/to_send[45]} {realSdPlayer/fastSender/to_send[46]} {realSdPlayer/fastSender/to_send[47]}]]
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connect_debug_port u_ila_0/probe19 [get_nets [list realSdPlayer/send_command_ready_fast]]
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connect_debug_port u_ila_0/probe21 [get_nets [list realSdPlayer/send_command_start_fast]]
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set_property MARK_DEBUG true [get_nets realSdPlayer/sd_cmd_OBUF]
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list CLK100MHZ_IBUF_BUFG]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 8 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {audioOutput/D[0]} {audioOutput/D[1]} {audioOutput/D[2]} {audioOutput/D[3]} {audioOutput/D[4]} {audioOutput/D[5]} {audioOutput/D[6]} {audioOutput/D[7]}]]
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set_property port_width 6 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {realSdPlayer/next_state[0]} {realSdPlayer/next_state[1]} {realSdPlayer/next_state[2]} {realSdPlayer/next_state[3]} {realSdPlayer/next_state[4]} {realSdPlayer/next_state[5]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 18 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {romSdPlayer/in7[1]} {romSdPlayer/in7[2]} {romSdPlayer/in7[3]} {romSdPlayer/in7[4]} {romSdPlayer/in7[5]} {romSdPlayer/in7[6]} {romSdPlayer/in7[7]} {romSdPlayer/in7[8]} {romSdPlayer/in7[9]} {romSdPlayer/in7[10]} {romSdPlayer/in7[11]} {romSdPlayer/in7[12]} {romSdPlayer/in7[13]} {romSdPlayer/in7[14]} {romSdPlayer/in7[15]} {romSdPlayer/in7[16]} {romSdPlayer/in7[17]} {romSdPlayer/in7[18]}]]
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set_property port_width 6 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {realSdPlayer/state[0]} {realSdPlayer/state[1]} {realSdPlayer/state[2]} {realSdPlayer/state[3]} {realSdPlayer/state[4]} {realSdPlayer/state[5]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 8 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {romSdPlayer/rom_data[0]} {romSdPlayer/rom_data[1]} {romSdPlayer/rom_data[2]} {romSdPlayer/rom_data[3]} {romSdPlayer/rom_data[4]} {romSdPlayer/rom_data[5]} {romSdPlayer/rom_data[6]} {romSdPlayer/rom_data[7]}]]
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set_property port_width 11 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {realSdPlayer/dataHandler/buffer\\.addra[0]} {realSdPlayer/dataHandler/buffer\\.addra[1]} {realSdPlayer/dataHandler/buffer\\.addra[2]} {realSdPlayer/dataHandler/buffer\\.addra[3]} {realSdPlayer/dataHandler/buffer\\.addra[4]} {realSdPlayer/dataHandler/buffer\\.addra[5]} {realSdPlayer/dataHandler/buffer\\.addra[6]} {realSdPlayer/dataHandler/buffer\\.addra[7]} {realSdPlayer/dataHandler/buffer\\.addra[8]} {realSdPlayer/dataHandler/buffer\\.addra[9]} {realSdPlayer/dataHandler/buffer\\.addra[10]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 11 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {romSdPlayer/audio_interface\\.addra[0]} {romSdPlayer/audio_interface\\.addra[1]} {romSdPlayer/audio_interface\\.addra[2]} {romSdPlayer/audio_interface\\.addra[3]} {romSdPlayer/audio_interface\\.addra[4]} {romSdPlayer/audio_interface\\.addra[5]} {romSdPlayer/audio_interface\\.addra[6]} {romSdPlayer/audio_interface\\.addra[7]} {romSdPlayer/audio_interface\\.addra[8]} {romSdPlayer/audio_interface\\.addra[9]} {romSdPlayer/audio_interface\\.addra[10]}]]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {realSdPlayer/arg[0]} {realSdPlayer/arg[1]} {realSdPlayer/arg[2]} {realSdPlayer/arg[3]} {realSdPlayer/arg[4]} {realSdPlayer/arg[5]} {realSdPlayer/arg[6]} {realSdPlayer/arg[7]} {realSdPlayer/arg[8]} {realSdPlayer/arg[9]} {realSdPlayer/arg[10]} {realSdPlayer/arg[11]} {realSdPlayer/arg[12]} {realSdPlayer/arg[13]} {realSdPlayer/arg[14]} {realSdPlayer/arg[15]} {realSdPlayer/arg[16]} {realSdPlayer/arg[17]} {realSdPlayer/arg[18]} {realSdPlayer/arg[19]} {realSdPlayer/arg[20]} {realSdPlayer/arg[21]} {realSdPlayer/arg[22]} {realSdPlayer/arg[23]} {realSdPlayer/arg[24]} {realSdPlayer/arg[25]} {realSdPlayer/arg[26]} {realSdPlayer/arg[27]} {realSdPlayer/arg[28]} {realSdPlayer/arg[29]} {realSdPlayer/arg[30]} {realSdPlayer/arg[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {audioOutput/pulse_counter_reg[0]} {audioOutput/pulse_counter_reg[1]} {audioOutput/pulse_counter_reg[2]} {audioOutput/pulse_counter_reg[3]} {audioOutput/pulse_counter_reg[4]} {audioOutput/pulse_counter_reg[5]} {audioOutput/pulse_counter_reg[6]} {audioOutput/pulse_counter_reg[7]}]]
|
||||
set_property port_width 48 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {realSdPlayer/received_data[0]} {realSdPlayer/received_data[1]} {realSdPlayer/received_data[2]} {realSdPlayer/received_data[3]} {realSdPlayer/received_data[4]} {realSdPlayer/received_data[5]} {realSdPlayer/received_data[6]} {realSdPlayer/received_data[7]} {realSdPlayer/received_data[8]} {realSdPlayer/received_data[9]} {realSdPlayer/received_data[10]} {realSdPlayer/received_data[11]} {realSdPlayer/received_data[12]} {realSdPlayer/received_data[13]} {realSdPlayer/received_data[14]} {realSdPlayer/received_data[15]} {realSdPlayer/received_data[16]} {realSdPlayer/received_data[17]} {realSdPlayer/received_data[18]} {realSdPlayer/received_data[19]} {realSdPlayer/received_data[20]} {realSdPlayer/received_data[21]} {realSdPlayer/received_data[22]} {realSdPlayer/received_data[23]} {realSdPlayer/received_data[24]} {realSdPlayer/received_data[25]} {realSdPlayer/received_data[26]} {realSdPlayer/received_data[27]} {realSdPlayer/received_data[28]} {realSdPlayer/received_data[29]} {realSdPlayer/received_data[30]} {realSdPlayer/received_data[31]} {realSdPlayer/received_data[32]} {realSdPlayer/received_data[33]} {realSdPlayer/received_data[34]} {realSdPlayer/received_data[35]} {realSdPlayer/received_data[36]} {realSdPlayer/received_data[37]} {realSdPlayer/received_data[38]} {realSdPlayer/received_data[39]} {realSdPlayer/received_data[40]} {realSdPlayer/received_data[41]} {realSdPlayer/received_data[42]} {realSdPlayer/received_data[43]} {realSdPlayer/received_data[44]} {realSdPlayer/received_data[45]} {realSdPlayer/received_data[46]} {realSdPlayer/received_data[47]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 19 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {romSdPlayer/xpm_memory_sprom_inst/addra[0]} {romSdPlayer/xpm_memory_sprom_inst/addra[1]} {romSdPlayer/xpm_memory_sprom_inst/addra[2]} {romSdPlayer/xpm_memory_sprom_inst/addra[3]} {romSdPlayer/xpm_memory_sprom_inst/addra[4]} {romSdPlayer/xpm_memory_sprom_inst/addra[5]} {romSdPlayer/xpm_memory_sprom_inst/addra[6]} {romSdPlayer/xpm_memory_sprom_inst/addra[7]} {romSdPlayer/xpm_memory_sprom_inst/addra[8]} {romSdPlayer/xpm_memory_sprom_inst/addra[9]} {romSdPlayer/xpm_memory_sprom_inst/addra[10]} {romSdPlayer/xpm_memory_sprom_inst/addra[11]} {romSdPlayer/xpm_memory_sprom_inst/addra[12]} {romSdPlayer/xpm_memory_sprom_inst/addra[13]} {romSdPlayer/xpm_memory_sprom_inst/addra[14]} {romSdPlayer/xpm_memory_sprom_inst/addra[15]} {romSdPlayer/xpm_memory_sprom_inst/addra[16]} {romSdPlayer/xpm_memory_sprom_inst/addra[17]} {romSdPlayer/xpm_memory_sprom_inst/addra[18]}]]
|
||||
set_property port_width 48 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {realSdPlayer/slowSender/to_send[0]} {realSdPlayer/slowSender/to_send[1]} {realSdPlayer/slowSender/to_send[2]} {realSdPlayer/slowSender/to_send[3]} {realSdPlayer/slowSender/to_send[4]} {realSdPlayer/slowSender/to_send[5]} {realSdPlayer/slowSender/to_send[6]} {realSdPlayer/slowSender/to_send[7]} {realSdPlayer/slowSender/to_send[8]} {realSdPlayer/slowSender/to_send[9]} {realSdPlayer/slowSender/to_send[10]} {realSdPlayer/slowSender/to_send[11]} {realSdPlayer/slowSender/to_send[12]} {realSdPlayer/slowSender/to_send[13]} {realSdPlayer/slowSender/to_send[14]} {realSdPlayer/slowSender/to_send[15]} {realSdPlayer/slowSender/to_send[16]} {realSdPlayer/slowSender/to_send[17]} {realSdPlayer/slowSender/to_send[18]} {realSdPlayer/slowSender/to_send[19]} {realSdPlayer/slowSender/to_send[20]} {realSdPlayer/slowSender/to_send[21]} {realSdPlayer/slowSender/to_send[22]} {realSdPlayer/slowSender/to_send[23]} {realSdPlayer/slowSender/to_send[24]} {realSdPlayer/slowSender/to_send[25]} {realSdPlayer/slowSender/to_send[26]} {realSdPlayer/slowSender/to_send[27]} {realSdPlayer/slowSender/to_send[28]} {realSdPlayer/slowSender/to_send[29]} {realSdPlayer/slowSender/to_send[30]} {realSdPlayer/slowSender/to_send[31]} {realSdPlayer/slowSender/to_send[32]} {realSdPlayer/slowSender/to_send[33]} {realSdPlayer/slowSender/to_send[34]} {realSdPlayer/slowSender/to_send[35]} {realSdPlayer/slowSender/to_send[36]} {realSdPlayer/slowSender/to_send[37]} {realSdPlayer/slowSender/to_send[38]} {realSdPlayer/slowSender/to_send[39]} {realSdPlayer/slowSender/to_send[40]} {realSdPlayer/slowSender/to_send[41]} {realSdPlayer/slowSender/to_send[42]} {realSdPlayer/slowSender/to_send[43]} {realSdPlayer/slowSender/to_send[44]} {realSdPlayer/slowSender/to_send[45]} {realSdPlayer/slowSender/to_send[46]} {realSdPlayer/slowSender/to_send[47]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 10 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {audioBuffer/buffer/addrb[0]} {audioBuffer/buffer/addrb[1]} {audioBuffer/buffer/addrb[2]} {audioBuffer/buffer/addrb[3]} {audioBuffer/buffer/addrb[4]} {audioBuffer/buffer/addrb[5]} {audioBuffer/buffer/addrb[6]} {audioBuffer/buffer/addrb[7]} {audioBuffer/buffer/addrb[8]} {audioBuffer/buffer/addrb[9]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {realSdPlayer/dataHandler/buffer\\.dina[0]} {realSdPlayer/dataHandler/buffer\\.dina[1]} {realSdPlayer/dataHandler/buffer\\.dina[2]} {realSdPlayer/dataHandler/buffer\\.dina[3]} {realSdPlayer/dataHandler/buffer\\.dina[4]} {realSdPlayer/dataHandler/buffer\\.dina[5]} {realSdPlayer/dataHandler/buffer\\.dina[6]} {realSdPlayer/dataHandler/buffer\\.dina[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list audioOutput/AUD_PWM_TRI]]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {realSdPlayer/cmd[0]} {realSdPlayer/cmd[1]} {realSdPlayer/cmd[2]} {realSdPlayer/cmd[3]} {realSdPlayer/cmd[4]} {realSdPlayer/cmd[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list romSdPlayer/rom_addr]]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {realSdPlayer/dataHandler/buffer\\.address_half}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {realSdPlayer/dataHandler/buffer\\.clka}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {realSdPlayer/dataHandler/buffer\\.ena}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list realSdPlayer/fast_clk]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list realSdPlayer/fast_clk_enable]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list realSdPlayer/read_command_listen]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list realSdPlayer/read_command_received]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list reset]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list realSdPlayer/sd_data]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list realSdPlayer/send_command_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list realSdPlayer/send_command_start]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list realSdPlayer/slowSender/send_sd_cmd]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list realSdPlayer/slow_clk]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list realSdPlayer/stored_sd_cmd]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
|
||||
57
SDVD.xpr
57
SDVD.xpr
@ -45,7 +45,7 @@
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
|
||||
<Option Name="ActiveSimSet" Val="read_data_tb"/>
|
||||
<Option Name="ActiveSimSet" Val="sd_controller_tb"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
|
||||
@ -61,7 +61,7 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="nexys-a7-100t"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="201"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="211"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
@ -230,6 +230,13 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/design/sd/sd_controller.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="nexys_a7_top"/>
|
||||
@ -459,6 +466,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="crc_gen_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/crc_gen_tb" RelGenDir="$PGENDIR/crc_gen_tb">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/verification/sd/rom_sd_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -498,6 +506,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="send_command_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/send_command_tb" RelGenDir="$PGENDIR/send_command_tb">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/verification/sd/send_command_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -524,6 +533,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="read_command_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/read_command_tb" RelGenDir="$PGENDIR/read_command_tb">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/verification/sd/read_command_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -556,6 +566,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="read_data_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/read_data_tb" RelGenDir="$PGENDIR/read_data_tb">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/verification/sd/read_data_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@ -587,6 +598,38 @@
|
||||
<Option Name="xsim.simulate.runtime" Val="1s"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sd_controller_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sd_controller_tb" RelGenDir="$PGENDIR/sd_controller_tb">
|
||||
<File Path="$PPRDIR/verification/sd/sd_controller_tb.sv">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/verification/waveform_configs/sd_controller_tb_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="sd_controller_tb"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/verification/waveform_configs/sd_controller_tb_behav.wcfg"/>
|
||||
<Option Name="CosimPdi" Val=""/>
|
||||
<Option Name="CosimPlatform" Val=""/>
|
||||
<Option Name="CosimElf" Val=""/>
|
||||
<Option Name="xsim.simulate.runtime" Val="1s"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@ -612,9 +655,7 @@
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@ -622,11 +663,9 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
@ -6,14 +6,20 @@ parameter DIVISOR;
|
||||
|
||||
logic [$clog2(DIVISOR)-1:0] counter;
|
||||
|
||||
logic set;
|
||||
|
||||
// clock will be high for about half of the cycle, depending on integer
|
||||
// rounding
|
||||
// OOPS this makes it combinational
|
||||
//assign oclk = counter < (DIVISOR/2);
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset)
|
||||
// modular clock has to keep ticking through reset
|
||||
// so everything with a synchronous reset actually works
|
||||
if (reset && !set) begin
|
||||
counter <= DIVISOR-1;
|
||||
set <= 1;
|
||||
end
|
||||
else if (counter == 0)
|
||||
counter <= DIVISOR-1;
|
||||
else
|
||||
|
||||
@ -15,7 +15,11 @@ module nexys_a7_top(
|
||||
output logic AUD_PWM, AUD_SD,
|
||||
output logic CA,CB,CC,CD,CE,CF,CG,
|
||||
output logic [7:0] AN,
|
||||
output wire LED[0:0]
|
||||
output wire LED[0:0],
|
||||
output wire SD_RESET,SD_SCK,
|
||||
inout wire [3:0] SD_DAT,
|
||||
inout wire SD_CMD,
|
||||
input wire SD_CD
|
||||
);
|
||||
|
||||
// Active high reset
|
||||
@ -51,7 +55,9 @@ logic playing;
|
||||
assign LED[0] = playing;
|
||||
assign AUD_SD = playing;
|
||||
|
||||
low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
|
||||
low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, 'z, clk_10hz, seconds_pulse);
|
||||
|
||||
modular_clock_gen #(100_000) anodeClock(CLK100MHZ, reset, clk_1khz);
|
||||
|
||||
// Create a clock with a divisor of 2083, making ~48khz
|
||||
modular_clock_gen #(2083) audioClock(CLK100MHZ, reset, clk_48khz);
|
||||
@ -102,7 +108,35 @@ audio_buffer audioBuffer(
|
||||
audio_interface.receiver
|
||||
);
|
||||
|
||||
rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
|
||||
`ifdef ROM
|
||||
rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
|
||||
assign {SD_RESET,SD_DAT,SD_CMD,SD_SCK} = 'z;
|
||||
`else
|
||||
// Power the sd slot
|
||||
assign SD_RESET = 0;
|
||||
// We don't use more than one dat line
|
||||
assign SD_DAT[3:1] = 'z;
|
||||
logic clk_100khz;
|
||||
logic clk_25mhz;
|
||||
// Actually 200khz now
|
||||
// 200khz is slightly unstable??????
|
||||
modular_clock_gen #(1000) slowSdClock(CLK100MHZ, reset, clk_100khz);
|
||||
// Try clocking this slower than max speed
|
||||
// To see if that makes it actually work ...
|
||||
modular_clock_gen #(1000) fastSdClock(CLK100MHZ, reset, clk_25mhz);
|
||||
sd_controller realSdPlayer(
|
||||
clk_100khz,
|
||||
clk_25mhz,
|
||||
CLK100MHZ,
|
||||
reset,
|
||||
SD_DAT[0],
|
||||
SD_CMD,
|
||||
sd_ready,
|
||||
SD_SCK,
|
||||
audio_interface.driver
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -9,14 +9,21 @@ module read_command(
|
||||
// This has to be large enough to capture each possible response
|
||||
output logic [135:0] out_data
|
||||
);
|
||||
|
||||
enum logic [2:0] {IDLE,START,LISTEN,RECEIVING,DONE} state, next_state;
|
||||
|
||||
// This should be large enough to capture the largest 136-bit response
|
||||
logic [$clog2(136):0] counter;
|
||||
logic [135:0] data_reg;
|
||||
logic received_reg;
|
||||
|
||||
logic [2:0] response_type_reg;
|
||||
|
||||
// oops this was set a cycle before the data was actually ready
|
||||
// and if it's just a reg it holds for too long
|
||||
// use both for maximum reactivity
|
||||
assign received = received_reg && !listen;
|
||||
|
||||
always_comb begin
|
||||
case (state)
|
||||
IDLE:
|
||||
@ -54,7 +61,8 @@ always_ff @(posedge clk) begin
|
||||
case (state)
|
||||
IDLE:
|
||||
begin
|
||||
received <= 0;
|
||||
// This defaulted to 1 ... oops
|
||||
received_reg <= 0;
|
||||
out_data <= 0;
|
||||
if (listen)
|
||||
response_type_reg <= response_type;
|
||||
@ -62,11 +70,12 @@ always_ff @(posedge clk) begin
|
||||
|
||||
START:
|
||||
begin
|
||||
received_reg <= 0;
|
||||
// off-by-one/cycle timing issues accumulated to a counter offset
|
||||
// of 3.
|
||||
counter <= get_bits(response_type_reg) - 3;
|
||||
// 3 in simulation, 2 in reality????
|
||||
counter <= get_bits(response_type_reg) - 2;
|
||||
data_reg <= 0;
|
||||
received <= 0;
|
||||
end
|
||||
|
||||
LISTEN:
|
||||
@ -83,10 +92,12 @@ always_ff @(posedge clk) begin
|
||||
|
||||
DONE:
|
||||
begin
|
||||
received <= 1;
|
||||
out_data <= data_reg;
|
||||
if (listen)
|
||||
received_reg <= 1;
|
||||
if (listen) begin
|
||||
received_reg <= 0;
|
||||
response_type_reg <= response_type;
|
||||
end
|
||||
end
|
||||
|
||||
default: ;
|
||||
|
||||
@ -5,6 +5,7 @@ module read_data(
|
||||
input clk,
|
||||
input reset,
|
||||
input sd_data,
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
audio_buffer_interface.driver buffer
|
||||
);
|
||||
// Block data is a start bit, 512 bytes sent msb first, then a CRC16 and end
|
||||
|
||||
391
design/sd/sd_controller.sv
Normal file
391
design/sd/sd_controller.sv
Normal file
@ -0,0 +1,391 @@
|
||||
/****
|
||||
* sd_controller.sv - Initializes and reads data off an sd card, feeding it
|
||||
* into the audio buffer
|
||||
*
|
||||
* @author: Waylon Cude, Dilanthi Prentice
|
||||
* @date: 6/12/25
|
||||
*
|
||||
* **/
|
||||
module sd_controller(
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
input logic slow_clk,
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
input logic fast_clk,
|
||||
input logic crc_clk,
|
||||
input logic reset,
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
input logic sd_data,
|
||||
inout logic sd_cmd,
|
||||
output logic ready,
|
||||
output wire clk,
|
||||
|
||||
audio_buffer_interface.driver buffer
|
||||
);
|
||||
// NOTE: this gets encoded as one-hot, even if in here I set it as a logic[5:0]
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
enum logic [5:0] {
|
||||
INIT,WAIT,SEND_CMD0,WAIT_CMD0,DELAY_CMD0, // last 4
|
||||
SEND_CMD8,WAIT_CMD8,LISTEN_RESPONSE_CMD8,WAIT_RESPONSE_CMD8, // last 8
|
||||
SEND_CMD55,WAIT_CMD55,LISTEN_RESPONSE_CMD55,WAIT_RESPONSE_CMD55, // last 12
|
||||
SEND_ACMD41,WAIT_ACMD41,LISTEN_RESPONSE_ACMD41,WAIT_RESPONSE_ACMD41,ACMD41_DELAY, //17
|
||||
SEND_CMD2,WAIT_CMD2,LISTEN_RESPONSE_CMD2,WAIT_RESPONSE_CMD2, //21
|
||||
SEND_CMD3,WAIT_CMD3,LISTEN_RESPONSE_CMD3,WAIT_RESPONSE_CMD3, //25
|
||||
SEND_CMD7,WAIT_CMD7,LISTEN_RESPONSE_CMD7,WAIT_RESPONSE_CMD7, //29
|
||||
READY_TO_TRANSMIT,
|
||||
TRANSMIT,WAIT_TRANSMIT,WAIT_END,FINISH_TRANSMIT,
|
||||
TRANSMIT2,WAIT_TRANSMIT2,WAIT_END2,FINISH_TRANSMIT2,
|
||||
WAIT_FOR_BUFFER
|
||||
} state, next_state;
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic fast_clk_enable;
|
||||
assign clk = fast_clk_enable ? fast_clk : slow_clk;
|
||||
|
||||
logic [$clog2(4114):0] counter;
|
||||
logic sd_buffer_half;
|
||||
logic [31:0] address;
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic send_command_start;//, send_command_start_fast;
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic [5:0] cmd;
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic [31:0] arg;
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
wire send_command_ready;//, send_command_ready_fast;
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic stored_sd_cmd;
|
||||
|
||||
// This needs to swap speeds
|
||||
send_command slowSender(
|
||||
clk,
|
||||
crc_clk,
|
||||
reset,
|
||||
send_command_start,
|
||||
cmd,
|
||||
arg,
|
||||
send_command_ready,
|
||||
sd_cmd);
|
||||
|
||||
//send_command fastSender(
|
||||
// fast_clk,
|
||||
// crc_clk,
|
||||
// reset,
|
||||
// send_command_start_fast,
|
||||
// cmd,
|
||||
// arg,
|
||||
// send_command_ready_fast,
|
||||
// sd_cmd);
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic read_command_listen;
|
||||
logic [2:0] response_type;
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
wire read_command_received;
|
||||
wire [135:0] out_data;
|
||||
|
||||
// Hopefully this doesn't get optimized out...
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic [47:0] received_data;
|
||||
assign received_data = out_data[47:0];
|
||||
|
||||
// This doesn't need to swap speeds as we ignore responses to CMD17
|
||||
read_command slowReader(
|
||||
slow_clk,
|
||||
reset,
|
||||
read_command_listen,
|
||||
response_type,
|
||||
sd_cmd,
|
||||
read_command_received,
|
||||
out_data
|
||||
);
|
||||
|
||||
// The data line is only ever used at fast_clk speeds
|
||||
read_data dataHandler(
|
||||
fast_clk,
|
||||
reset,
|
||||
sd_data,
|
||||
buffer
|
||||
);
|
||||
|
||||
//always_ff @(posedge crc_clk) begin
|
||||
// stored_sd_cmd <= sd_cmd;
|
||||
//end
|
||||
|
||||
// Next state logic
|
||||
always_comb begin
|
||||
case (state)
|
||||
INIT: next_state=WAIT;
|
||||
WAIT:
|
||||
if (counter==0)
|
||||
next_state=SEND_CMD0;
|
||||
else
|
||||
next_state=WAIT;
|
||||
SEND_CMD0:
|
||||
next_state=WAIT_CMD0;
|
||||
WAIT_CMD0:
|
||||
if (send_command_ready)
|
||||
next_state=DELAY_CMD0;
|
||||
else
|
||||
next_state=WAIT_CMD0;
|
||||
DELAY_CMD0:
|
||||
if (counter == 0)
|
||||
next_state=SEND_CMD8;
|
||||
else
|
||||
next_state=DELAY_CMD0;
|
||||
// These state transitions are all very similar, this probably could
|
||||
// be a macro
|
||||
SEND_CMD8:
|
||||
next_state=WAIT_CMD8;
|
||||
WAIT_CMD8:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_CMD8;
|
||||
else
|
||||
next_state=WAIT_CMD8;
|
||||
LISTEN_RESPONSE_CMD8:
|
||||
next_state=WAIT_RESPONSE_CMD8;
|
||||
WAIT_RESPONSE_CMD8:
|
||||
if (read_command_received)
|
||||
next_state=SEND_CMD55;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_CMD8;
|
||||
SEND_CMD2:
|
||||
next_state=WAIT_CMD2;
|
||||
WAIT_CMD2:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_CMD2;
|
||||
else
|
||||
next_state=WAIT_CMD2;
|
||||
LISTEN_RESPONSE_CMD2:
|
||||
next_state=WAIT_RESPONSE_CMD2;
|
||||
WAIT_RESPONSE_CMD2:
|
||||
if (read_command_received)
|
||||
next_state=SEND_CMD3;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_CMD2;
|
||||
SEND_CMD3:
|
||||
next_state=WAIT_CMD3;
|
||||
WAIT_CMD3:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_CMD3;
|
||||
else
|
||||
next_state=WAIT_CMD3;
|
||||
LISTEN_RESPONSE_CMD3:
|
||||
next_state=WAIT_RESPONSE_CMD3;
|
||||
WAIT_RESPONSE_CMD3:
|
||||
if (read_command_received)
|
||||
next_state=SEND_CMD7;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_CMD3;
|
||||
SEND_CMD7:
|
||||
next_state=WAIT_CMD7;
|
||||
WAIT_CMD7:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_CMD7;
|
||||
else
|
||||
next_state=WAIT_CMD7;
|
||||
LISTEN_RESPONSE_CMD7:
|
||||
next_state=WAIT_RESPONSE_CMD7;
|
||||
WAIT_RESPONSE_CMD7:
|
||||
if (read_command_received)
|
||||
next_state=READY_TO_TRANSMIT;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_CMD7;
|
||||
|
||||
|
||||
SEND_CMD55:
|
||||
next_state=WAIT_CMD55;
|
||||
WAIT_CMD55:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_CMD55;
|
||||
else
|
||||
next_state=WAIT_CMD55;
|
||||
LISTEN_RESPONSE_CMD55:
|
||||
next_state=WAIT_RESPONSE_CMD55;
|
||||
WAIT_RESPONSE_CMD55:
|
||||
if (read_command_received)
|
||||
next_state=SEND_ACMD41;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_CMD55;
|
||||
SEND_ACMD41:
|
||||
next_state=WAIT_ACMD41;
|
||||
WAIT_ACMD41:
|
||||
if (send_command_ready)
|
||||
next_state=LISTEN_RESPONSE_ACMD41;
|
||||
else
|
||||
next_state=WAIT_ACMD41;
|
||||
LISTEN_RESPONSE_ACMD41:
|
||||
next_state=WAIT_RESPONSE_ACMD41;
|
||||
WAIT_RESPONSE_ACMD41:
|
||||
if (read_command_received && !out_data[39])
|
||||
next_state=ACMD41_DELAY;
|
||||
else if (read_command_received && out_data[39])
|
||||
next_state=SEND_CMD2;
|
||||
else
|
||||
next_state=WAIT_RESPONSE_ACMD41;
|
||||
ACMD41_DELAY:
|
||||
if (counter == 0)
|
||||
next_state=SEND_CMD55;
|
||||
else
|
||||
next_state=ACMD41_DELAY;
|
||||
|
||||
READY_TO_TRANSMIT:
|
||||
next_state=TRANSMIT;
|
||||
TRANSMIT:
|
||||
next_state=WAIT_TRANSMIT;
|
||||
WAIT_TRANSMIT:
|
||||
if (sd_data==0)
|
||||
next_state=WAIT_END;
|
||||
else
|
||||
next_state=WAIT_TRANSMIT;
|
||||
WAIT_END:
|
||||
if (counter==0)
|
||||
next_state=FINISH_TRANSMIT;
|
||||
else
|
||||
next_state=WAIT_END;
|
||||
FINISH_TRANSMIT:
|
||||
next_state=TRANSMIT2;
|
||||
TRANSMIT2:
|
||||
next_state=WAIT_TRANSMIT2;
|
||||
WAIT_TRANSMIT2:
|
||||
if (sd_data==0)
|
||||
next_state=WAIT_END2;
|
||||
else
|
||||
next_state=WAIT_TRANSMIT2;
|
||||
WAIT_END2:
|
||||
if (counter==0)
|
||||
next_state=FINISH_TRANSMIT2;
|
||||
else
|
||||
next_state=WAIT_END2;
|
||||
FINISH_TRANSMIT2:
|
||||
next_state=WAIT_FOR_BUFFER;
|
||||
|
||||
WAIT_FOR_BUFFER:
|
||||
if (sd_buffer_half==buffer.address_half)
|
||||
next_state=WAIT_FOR_BUFFER;
|
||||
else
|
||||
next_state=TRANSMIT;
|
||||
default:
|
||||
next_state=INIT;
|
||||
endcase
|
||||
|
||||
end
|
||||
// This could mostly swap speeds ... however detecting the data line going low
|
||||
// would not work
|
||||
always_ff @(posedge clk) begin
|
||||
stored_sd_cmd <= sd_cmd;
|
||||
// Transition states
|
||||
if (reset)
|
||||
state <= INIT;
|
||||
else
|
||||
state <= next_state;
|
||||
|
||||
// Sequential outputs/logic
|
||||
case (state)
|
||||
INIT: begin
|
||||
counter <= 80;
|
||||
fast_clk_enable <= 0;
|
||||
end
|
||||
SEND_CMD0: begin
|
||||
cmd<=0;
|
||||
arg<=0;
|
||||
send_command_start <= 1;
|
||||
end
|
||||
WAIT_CMD0: begin
|
||||
counter<=20;
|
||||
send_command_start<=0;
|
||||
end
|
||||
SEND_CMD8: begin
|
||||
cmd <=8;
|
||||
arg <='h1AA;
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_CMD8: begin
|
||||
response_type <= 7;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
SEND_CMD55: begin
|
||||
cmd <= 55;
|
||||
arg <= 0;
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_CMD55: begin
|
||||
response_type <= 1;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
SEND_ACMD41: begin
|
||||
cmd <= 41;
|
||||
arg <= 'h40100000;
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_ACMD41: begin
|
||||
response_type <= 3;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
WAIT_RESPONSE_ACMD41: begin
|
||||
read_command_listen<=0;
|
||||
counter<=100;
|
||||
end
|
||||
SEND_CMD2: begin
|
||||
cmd <= 2;
|
||||
arg <= 0;
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_CMD2: begin
|
||||
response_type <= 2;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
SEND_CMD3: begin
|
||||
cmd <= 3;
|
||||
arg <= 0;
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_CMD3: begin
|
||||
response_type <= 6;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
SEND_CMD7: begin
|
||||
cmd <= 7;
|
||||
arg <= {out_data[39:24],16'h0000};
|
||||
send_command_start <=1;
|
||||
end
|
||||
LISTEN_RESPONSE_CMD7: begin
|
||||
response_type <= 1;
|
||||
read_command_listen <= 1;
|
||||
end
|
||||
READY_TO_TRANSMIT: begin
|
||||
fast_clk_enable <= 1;
|
||||
address <= 0;
|
||||
sd_buffer_half <= 0;
|
||||
end
|
||||
TRANSMIT, TRANSMIT2: begin
|
||||
cmd <= 17;
|
||||
arg <= address;
|
||||
send_command_start <= 1;
|
||||
end
|
||||
WAIT_TRANSMIT, WAIT_TRANSMIT2: begin
|
||||
send_command_start <= 0;
|
||||
counter <= 411;
|
||||
end
|
||||
FINISH_TRANSMIT:
|
||||
address <= address +1;
|
||||
FINISH_TRANSMIT2: begin
|
||||
address <= address +1;
|
||||
sd_buffer_half <= ~sd_buffer_half;
|
||||
end
|
||||
WAIT_FOR_BUFFER:
|
||||
ready <= 1;
|
||||
// The logic is simple enough in these to group them
|
||||
WAIT, DELAY_CMD0, ACMD41_DELAY, WAIT_END, WAIT_END2:
|
||||
counter <= counter - 1;
|
||||
WAIT_CMD8,WAIT_CMD55,WAIT_ACMD41,WAIT_CMD2,WAIT_CMD3,WAIT_CMD7:
|
||||
send_command_start<=0;
|
||||
WAIT_RESPONSE_CMD8,WAIT_RESPONSE_CMD55,WAIT_RESPONSE_CMD2,WAIT_RESPONSE_CMD3,
|
||||
WAIT_RESPONSE_CMD7:
|
||||
read_command_listen<=0;
|
||||
default: ;
|
||||
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@ -7,9 +7,9 @@ module send_command(
|
||||
input [5:0] command,
|
||||
input [31:0] arguments,
|
||||
output logic ready,
|
||||
output logic sd_cmd
|
||||
output wire sd_cmd
|
||||
);
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic [47:0] to_send;
|
||||
|
||||
logic crc_start;
|
||||
@ -18,6 +18,7 @@ logic [6:0] crc;
|
||||
|
||||
logic [$clog2(48):0] counter;
|
||||
|
||||
(* MARK_DEBUG = "TRUE" *)
|
||||
logic send_sd_cmd;
|
||||
|
||||
enum logic [2:0] {READY, SEND_CRC, DELAY, WAIT_CRC, SEND_DATA} cur_state, next_state;
|
||||
@ -45,7 +46,7 @@ always_comb begin
|
||||
else
|
||||
next_state = WAIT_CRC;
|
||||
SEND_DATA:
|
||||
if (counter != 0)
|
||||
if (counter != 1)
|
||||
next_state = SEND_DATA;
|
||||
else
|
||||
next_state = READY;
|
||||
@ -56,7 +57,9 @@ always_comb begin
|
||||
end
|
||||
|
||||
assign sd_cmd = send_sd_cmd ? 'z : 0;
|
||||
assign ready = (cur_state == READY);
|
||||
// BUG SPOTTED: Too slow, make the output more reactive
|
||||
// Added start input check to achieve this
|
||||
assign ready = (cur_state == READY && !start);
|
||||
// Sequential logic
|
||||
always_ff @(posedge clk) begin
|
||||
// Default to high-z
|
||||
@ -92,7 +95,6 @@ end
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) begin
|
||||
cur_state <= READY;
|
||||
counter <= 48;
|
||||
end
|
||||
else begin
|
||||
cur_state <= next_state;
|
||||
|
||||
@ -17,11 +17,15 @@ module display_anode_driver(
|
||||
output logic [7:0] AN,
|
||||
output logic [2:0] mux_select);
|
||||
|
||||
// Initialize this once, it can be free-running after
|
||||
logic started;
|
||||
|
||||
// This is just a shift register that drives each anode individually
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) begin
|
||||
AN <= '1 - 1;
|
||||
mux_select <= 0;
|
||||
started <= 1;
|
||||
end
|
||||
else begin
|
||||
AN <= {AN[6:0], AN[7]};
|
||||
|
||||
@ -30,6 +30,8 @@
|
||||
### command_sender
|
||||
- output ready signal was delay a cycle because it was set by sequential logic,
|
||||
detected in testing, changed it to a combinational output for 1 cycle speedup
|
||||
- counter was being set in multiple blocks, caught by synthesis
|
||||
- output phase too long, caught in hw
|
||||
|
||||
### read_command
|
||||
- response_type was not getting correctly stored/set, breaking the module
|
||||
@ -39,3 +41,9 @@
|
||||
## read_data
|
||||
- audio buffer address to write to was never changing, caught in simulation
|
||||
- some off-by-one errors in the byte shifting were found and corrected
|
||||
|
||||
### modular_clock
|
||||
- stopped ticking on reset
|
||||
- meant that every module using these clocks w/ a synchronous reset would get
|
||||
stuck and never reset
|
||||
- found during hw debugging
|
||||
|
||||
136
doc/sd_controller.gv
Normal file
136
doc/sd_controller.gv
Normal file
@ -0,0 +1,136 @@
|
||||
digraph sd_controller {
|
||||
// Rough steps
|
||||
INIT [shape=doublecircle, label="INIT\ncounter=80\nclk_source=slow"];
|
||||
node [shape=ellipse]
|
||||
// Tick at slow speed (100khz? 400khz?) for 80 ticks
|
||||
WAIT [label="WAIT\ncounter--"];
|
||||
// Send CMD0 with arg 0
|
||||
SEND_CMD0 [label="SEND_CMD0\ncmd=0\narg=0\nstart=1"];
|
||||
// There is no response to CMD0, so tick for 20 more cycles then send CMD8
|
||||
WAIT_CMD0 [label="WAIT_CMD0\ncounter=20\nstart=0"];
|
||||
DELAY_CMD0 [label="DELAY_CMD0\ncounter--"];
|
||||
// Send CMD8
|
||||
SEND_CMD8 [label="SEND_CMD8\ncmd=8\narg=0x1AA\nstart=1"];
|
||||
WAIT_CMD8 [label="WAIT_CMD8\nstart=0"];
|
||||
LISTEN_RESPONSE_CMD8 [label="LISTEN_RESPONSE_CMD8\nresponse_type=7\nread_command.listen=1"]
|
||||
WAIT_RESPONSE_CMD8 [label="WAIT_RESPONSE_CMD8\nread_command.listen=0"];
|
||||
|
||||
INIT -> WAIT;
|
||||
WAIT -> WAIT [label="counter!=0"];
|
||||
WAIT -> SEND_CMD0 [label="counter==0"];
|
||||
SEND_CMD0 -> WAIT_CMD0;
|
||||
WAIT_CMD0 -> DELAY_CMD0 [label="send_command.ready"];
|
||||
WAIT_CMD0 -> WAIT_CMD0 [label="!send_command.ready"]
|
||||
DELAY_CMD0 -> DELAY_CMD0 [label="counter!=0"];
|
||||
DELAY_CMD0 -> SEND_CMD8 [label="counter==0"]
|
||||
SEND_CMD8 -> WAIT_CMD8;
|
||||
WAIT_CMD8 -> WAIT_CMD8 [label="!send_command.ready"]
|
||||
WAIT_CMD8 -> LISTEN_RESPONSE_CMD8 [label="send_command.ready"]
|
||||
LISTEN_RESPONSE_CMD8 -> WAIT_RESPONSE_CMD8;
|
||||
WAIT_RESPONSE_CMD8 -> WAIT_RESPONSE_CMD8 [label="!read_command.received"]
|
||||
|
||||
// Send CMD55+CMD41 with arg 40100000 until card is ready
|
||||
SEND_CMD55 [label="SEND_CMD55\ncmd=55\narg=0\nstart=1"];
|
||||
WAIT_CMD55 [label="WAIT_CMD55\nstart=0"];
|
||||
LISTEN_RESPONSE_CMD55 [label="LISTEN_RESPONSE_CMD55\nresponse_type=1\nread_command.listen=1"]
|
||||
WAIT_RESPONSE_CMD55 [label="WAIT_RESPONSE_CMD55\nread_command.listen=0"]
|
||||
SEND_ACMD41 [label="SEND_ACMD41\ncmd=41\narg=0x40100000\nstart=1"];
|
||||
WAIT_ACMD41 [label="WAIT_ACMD41\nstart=0"];
|
||||
LISTEN_RESPONSE_ACMD41 [label="LISTEN_RESPONSE_ACMD41\nresponse_type=3\nread_command.listen=1"]
|
||||
WAIT_RESPONSE_ACMD41 [label="WAIT_RESPONSE_ACMD41\nread_command.listen=0\ncounter=100"];
|
||||
// Delay trying this again
|
||||
ACMD41_DELAY [label="ACMD41_DELAY\ncounter--"];
|
||||
// Card is ready when bit31 is high
|
||||
|
||||
WAIT_RESPONSE_CMD8 -> SEND_CMD55 [label="read_command.received"]
|
||||
SEND_CMD55 -> WAIT_CMD55;
|
||||
WAIT_CMD55 -> WAIT_CMD55 [label="!send_command.ready"];
|
||||
WAIT_CMD55 -> LISTEN_RESPONSE_CMD55 [label="send_command.ready"];
|
||||
LISTEN_RESPONSE_CMD55 -> WAIT_RESPONSE_CMD55;
|
||||
WAIT_RESPONSE_CMD55 -> WAIT_RESPONSE_CMD55 [label="!read_command.received"]
|
||||
WAIT_RESPONSE_CMD55 -> SEND_ACMD41 [label="read_command.received"]
|
||||
SEND_ACMD41 -> WAIT_ACMD41
|
||||
WAIT_ACMD41 -> WAIT_ACMD41 [label="!send_command.ready"]
|
||||
WAIT_ACMD41 -> LISTEN_RESPONSE_ACMD41[label="send_command.ready"]
|
||||
LISTEN_RESPONSE_ACMD41 -> WAIT_RESPONSE_ACMD41
|
||||
WAIT_RESPONSE_ACMD41 -> WAIT_RESPONSE_ACMD41 [label="!read_command.received"]
|
||||
WAIT_RESPONSE_ACMD41 -> ACMD41_DELAY [label="read_command.received && !out_data[39]"]
|
||||
ACMD41_DELAY -> ACMD41_DELAY [label="counter!=0"]
|
||||
ACMD41_DELAY -> SEND_CMD55 [label="counter==0"]
|
||||
|
||||
|
||||
// CMD2 with argument 0, dont need response
|
||||
SEND_CMD2 [label="SEND_CMD2\ncmd=2\narg=0\nsend_command.start=1"];
|
||||
WAIT_CMD2 [label="WAIT_CMD2\nsend_command.start=0"];
|
||||
LISTEN_RESPONSE_CMD2 [label="LISTEN_RESPONSE_CMD2\nresponse_type=2\nread_command.listen=1"];
|
||||
WAIT_RESPONSE_CMD2 [label="WAIT_RESPONSE_CMD2\nread_command.listen=0"];
|
||||
|
||||
WAIT_RESPONSE_ACMD41 -> SEND_CMD2 [label="read_command.received && out_data[39]"]
|
||||
SEND_CMD2 -> WAIT_CMD2;
|
||||
WAIT_CMD2 -> WAIT_CMD2 [label="!send_command.ready"]
|
||||
WAIT_CMD2 -> LISTEN_RESPONSE_CMD2 [label="send_command.ready"]
|
||||
LISTEN_RESPONSE_CMD2 -> WAIT_RESPONSE_CMD2;
|
||||
WAIT_RESPONSE_CMD2 -> WAIT_RESPONSE_CMD2 [label="!read_command.received"]
|
||||
|
||||
// CMD3 with argument 0 to get RCA
|
||||
SEND_CMD3 [label="SEND_CMD3\ncmd=3\narg=0\nsend_command.start=1"];
|
||||
WAIT_CMD3 [label="WAIT_CMD3\nsend_command.start=0"];
|
||||
LISTEN_RESPONSE_CMD3 [label="LISTEN_RESPONSE_CMD3\nresponse_type=6\nread_command.listen=1"];
|
||||
WAIT_RESPONSE_CMD3 [label="WAIT_RESPONSE_CMD3\nread_command.listen=0"];
|
||||
|
||||
WAIT_RESPONSE_CMD2 -> SEND_CMD3 [label="read_command.received"]
|
||||
SEND_CMD3 -> WAIT_CMD3
|
||||
WAIT_CMD3 -> WAIT_CMD3 [label="!send_command.ready"]
|
||||
WAIT_CMD3 -> LISTEN_RESPONSE_CMD3 [label="send_command.ready"]
|
||||
LISTEN_RESPONSE_CMD3 -> WAIT_RESPONSE_CMD3;
|
||||
WAIT_RESPONSE_CMD3 -> WAIT_RESPONSE_CMD3 [label="!read_command.received"]
|
||||
|
||||
// CMD7 to select the correct card given the RCA
|
||||
SEND_CMD7 [label="SEND_CMD7\ncmd=7\narg={out_data[39:24],16'h0000}\nsend_command.start=1"];
|
||||
WAIT_CMD7 [label="WAIT_CMD7\nsend_command.start=0"];
|
||||
LISTEN_RESPONSE_CMD7 [label="LISTEN_RESPONSE_CMD7\nresponse_type=1\nread_command.listen=1"];
|
||||
WAIT_RESPONSE_CMD7 [label="WAIT_RESPONSE_CMD7\nread_command.listen=0"];
|
||||
|
||||
WAIT_RESPONSE_CMD3 -> SEND_CMD7[label="read_command.received"]
|
||||
SEND_CMD7 -> WAIT_CMD7;
|
||||
WAIT_CMD7 -> WAIT_CMD7 [label="!send_command.ready"]
|
||||
WAIT_CMD7 -> LISTEN_RESPONSE_CMD7 [label="send_command.ready"]
|
||||
LISTEN_RESPONSE_CMD7 -> WAIT_RESPONSE_CMD7;
|
||||
WAIT_RESPONSE_CMD7 -> WAIT_RESPONSE_CMD7 [label="!read_command.ready"]
|
||||
|
||||
|
||||
// Now we can finally read blocks with CMD17
|
||||
// Swap over to the fast clock
|
||||
READY_TO_TRANSMIT [label="READY_TO_TRANSMIT\nclk_source=fast\naddress=0\nbuffer_half=0"];
|
||||
// There are two sets of states because we need to read two blocks at once
|
||||
TRANSMIT [label="TRANSMIT\ncmd=17\narg=address\nsend_command.start=1"];
|
||||
WAIT_TRANSMIT [label="WAIT_TRANSMIT\nsend_command.start=0\ncounter=4114"];
|
||||
WAIT_END [label="WAIT_END\ncounter--"];
|
||||
FINISH_TRANSMIT [label="FINISH_TRANSMIT\naddress++"]
|
||||
|
||||
TRANSMIT2 [label="TRANSMIT2\ncmd=17\narg=address\nsend_command.start=1"];
|
||||
WAIT_TRANSMIT2 [label="WAIT_TRANSMIT2\nsend_command.start=0\ncounter=4114"];
|
||||
WAIT_END2 [label="WAIT_END2\ncounter--"];
|
||||
FINISH_TRANSMIT2 [label="FINISH_TRANSMIT2\naddress++\nsd_buffer_half=!sd_buffer_half"]
|
||||
|
||||
// Wait for the buffer to be free, then go back to TRANSMIT
|
||||
WAIT_FOR_BUFFER [label="WAIT_FOR_BUFFER\nready=1"];
|
||||
|
||||
WAIT_RESPONSE_CMD7 -> READY_TO_TRANSMIT [label="read_command.ready"]
|
||||
READY_TO_TRANSMIT -> TRANSMIT;
|
||||
TRANSMIT -> WAIT_TRANSMIT;
|
||||
WAIT_TRANSMIT -> WAIT_TRANSMIT [label="sd_data==1"]
|
||||
WAIT_TRANSMIT -> WAIT_END [label="sd_data==0"]
|
||||
WAIT_END -> WAIT_END [label="counter!=0"]
|
||||
WAIT_END -> FINISH_TRANSMIT [label="counter==0"]
|
||||
FINISH_TRANSMIT -> TRANSMIT2;
|
||||
TRANSMIT2 -> WAIT_TRANSMIT2;
|
||||
WAIT_TRANSMIT2 -> WAIT_TRANSMIT2 [label="sd_data==1"]
|
||||
WAIT_TRANSMIT2 -> WAIT_END2 [label="sd_data==0"]
|
||||
WAIT_END2 -> WAIT_END2 [label="counter!=0"]
|
||||
WAIT_END2 -> FINISH_TRANSMIT2 [label="counter==0"]
|
||||
FINISH_TRANSMIT2 -> WAIT_FOR_BUFFER;
|
||||
|
||||
WAIT_FOR_BUFFER -> WAIT_FOR_BUFFER [label="sd_buffer_half==audio_buffer.address_half"];
|
||||
WAIT_FOR_BUFFER -> TRANSMIT [label="sd_buffer_half!=audio_buffer.address_half"];
|
||||
}
|
||||
BIN
doc/sd_controller.png
Normal file
BIN
doc/sd_controller.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 612 KiB |
BIN
roms/even_flow_16_full.raw
Normal file
BIN
roms/even_flow_16_full.raw
Normal file
Binary file not shown.
45
verification/sd/sd_controller_tb.sv
Normal file
45
verification/sd/sd_controller_tb.sv
Normal file
@ -0,0 +1,45 @@
|
||||
module sd_controller_tb;
|
||||
bit slow_clk,fast_clk,crc_clk;
|
||||
logic reset,sd_data;
|
||||
wire sd_cmd;
|
||||
wire ready;
|
||||
wire clk;
|
||||
audio_buffer_interface buffer ();
|
||||
|
||||
sd_controller dut (.buffer(buffer.driver), .*);
|
||||
|
||||
bit sd_write;
|
||||
|
||||
assign sd_cmd = sd_write ? 'z : 0;
|
||||
|
||||
initial forever #100 slow_clk = ~slow_clk;
|
||||
|
||||
initial forever #1 crc_clk = ~crc_clk;
|
||||
initial forever #10 fast_clk = ~fast_clk;
|
||||
|
||||
initial begin
|
||||
|
||||
sd_write = 1;
|
||||
reset = 1;
|
||||
repeat (2) @(posedge slow_clk);
|
||||
reset = 0;
|
||||
repeat (200) @(posedge slow_clk);
|
||||
send_response();
|
||||
|
||||
repeat (100) @(posedge slow_clk);
|
||||
send_response();
|
||||
repeat (100) @(posedge slow_clk);
|
||||
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
||||
task automatic send_response();
|
||||
for(int i=0;i<47;i++)
|
||||
@(posedge slow_clk) sd_write = 0;
|
||||
@(posedge slow_clk) sd_write = 1;
|
||||
endtask
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
67
verification/waveform_configs/sd_controller_tb_behav.wcfg
Normal file
67
verification/waveform_configs/sd_controller_tb_behav.wcfg
Normal file
@ -0,0 +1,67 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="sd_controller_tb_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="sd_controller_tb" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="41,685.336 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="44,957.696 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="0.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="469"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="172"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="11" />
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/slow_clk">
|
||||
<obj_property name="ElementShortName">slow_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">slow_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/fast_clk">
|
||||
<obj_property name="ElementShortName">fast_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">fast_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/crc_clk">
|
||||
<obj_property name="ElementShortName">crc_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">crc_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/reset">
|
||||
<obj_property name="ElementShortName">reset</obj_property>
|
||||
<obj_property name="ObjectShortName">reset</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/sd_data">
|
||||
<obj_property name="ElementShortName">sd_data</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_data</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/sd_cmd">
|
||||
<obj_property name="ElementShortName">sd_cmd</obj_property>
|
||||
<obj_property name="ObjectShortName">sd_cmd</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/ready">
|
||||
<obj_property name="ElementShortName">ready</obj_property>
|
||||
<obj_property name="ObjectShortName">ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/sd_controller_tb/dut/state">
|
||||
<obj_property name="ElementShortName">state[5:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">state[5:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/dut/sender/ready">
|
||||
<obj_property name="ElementShortName">ready</obj_property>
|
||||
<obj_property name="ObjectShortName">ready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/sd_controller_tb/dut/reader/received">
|
||||
<obj_property name="ElementShortName">received</obj_property>
|
||||
<obj_property name="ObjectShortName">received</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Loading…
x
Reference in New Issue
Block a user