added headers/ updated old ones

design/audio/audio_buffer.sv

@@ -1,6 +1,15 @@
+/****
+ * audio_buffer.sv - holds a 2KiB audio buffer of 16-bit pcm audio
+ *                   samples (with pcm being the audio format we are using)
+ *
+ * @author: Waylon Cude, Dilanthi
+ * @date: 6/12/2025
+ *
+ * */
 `ifdef VERILATOR
     `include "sdvd_defs.sv"
 `endif
+
 import sdvd_defs::SPEED;
 
 //this interfaces with block ram

design/audio/pwm.sv

@@ -1,8 +1,9 @@
 /****
- * pwm.sv - [must edit in future]
+ * pwm.sv - drives the pwm audio output on the FPGA given a single 16-bit
+ *          sample. 
  *
  * @author: Dilanthi Prentice, Waylon Cude
- * @date: [not sure when due yet]
+ * @date: 6-12-2025
  *
  *
  * */

design/debouncer.sv

@@ -1,3 +1,11 @@
+/***
+ * debouncer.sv - generates a debounced button press and turns it inot
+ *                a single pulse.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6-12-25
+ *
+ * */
 //NOTE: you should drive this with a slow clock to actually debounce input
 module debouncer(input logic clk, input reset, input source, output logic out);
 

design/low_freq_clock_gen.sv

@@ -1,3 +1,12 @@
+/****
+ * low_freq_clock_gen.sv - Generates different clock frequencies to drive
+ *                         different state machines and different parts of
+ *                         the design. 
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ * */
+
 `ifdef VERILATOR
     `include "sdvd_defs.sv"
 `endif

design/nexys_a7_top.sv

@@ -1,3 +1,10 @@
+/***
+ * nexys_a7_top.sv - top level design module specific to Nexys A7100T.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * **/
 `ifdef VERILATOR
     `include "sdvd_defs.sv"
 `endif

design/segment_display/display_anode_driver.sv

@@ -1,4 +1,16 @@
-// NOTE: This expects to be driven with a 100khz clock
+/***
+ * display_anode_driver.sv - Turns a single anode of a single digit at a time,
+ *                           rapidly rotating through all of them, generating
+ *                           a solid-looking display even though only one digit
+ *                           is on at a time.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6-12-2025
+ *
+ * */
+
+// NOTE: This expects to be driven with a 100khz clock but can be altered in
+// the nexys_a7_top.sv file.
 module display_anode_driver(
     input logic clk, 
     input logic reset, 

design/segment_display/display_converter.sv

@@ -1,12 +1,12 @@
 /**
 * display_converter.sv - decodes a 5 bit digit input into its seven segment
 *                        display equivalent using a lookup table. Display can
-*                        do 0 - 9, A - F, individual segmentsm and special
+*                        do 0 - 9, A - F, individual segments and special
 *                        characters.  
+*
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6/12/25
 *
-*
 ****/
 module display_converter(
     input logic [4:0] digit, 
@@ -16,6 +16,7 @@ module display_converter(
 localparam ROM_SIZE=32;
 
 //ROM lookup table for seven segment display
+//blanks are unused space we could add characters to. 
 localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
     7'b1111110, //0
     7'b0000110, //1
@@ -54,6 +55,7 @@ localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
     7'b0000000, //blank
     7'b0000000  //blank
 };
+
 //use digit input to index segment_rom lookup table.
 assign segment = segment_rom[digit];
 

design/segment_display/seconds_display.sv

@@ -1,10 +1,11 @@
 /***
-* seconds_display.sv - convert a seconds counter to a seven segement display.
+* seconds_display.sv - converts a five bit seconds counter to its seven segement display equivalent.
 *
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6/12/25
 *
 */
+
 module seconds_display
 (
     input [$clog2(60)-1:0] seconds,

verification/segment_display/seconds_display_tb.sv

@@ -1,3 +1,11 @@
+/****
+ * seconds_display_tb.sv - testbench for the seconds_display module.
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/2025
+ *
+ * */
+
 `timescale 1ns / 1ps
 module seconds_display_tb;
 int errors = 0;