33 lines
954 B
Systemverilog
33 lines
954 B
Systemverilog
/***
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* display_anode_driver.sv - Turns a single anode of a single digit at a time,
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* rapidly rotating through all of them, generating
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* a solid-looking display even though only one digit
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* is on at a time.
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*
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* @author: Waylon Cude, Dilanthi Prentice
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* @date: 6-12-2025
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*
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* */
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// NOTE: This expects to be driven with a 100khz clock but can be altered in
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// the nexys_a7_top.sv file.
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module display_anode_driver(
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input logic clk,
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input logic reset,
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output logic [7:0] AN,
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output logic [2:0] mux_select);
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// This is just a shift register that drives each anode individually
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always_ff @(posedge clk) begin
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if (reset) begin
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AN <= '1 - 1;
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mux_select <= 0;
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end
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else begin
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AN <= {AN[6:0], AN[7]};
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// Letting this overflow will automatically reset it
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mux_select <= mux_select + 1;
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end
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end
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endmodule
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