header for rom_sd.sv
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@ -1,5 +1,10 @@
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// A dummy sdcard module for testing the audio port
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/****
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* rom_sd.sv - reads audio data off a rom and feeds it to the audio buffer
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*
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* @author: Dilanthi Prentice, Waylon Cude
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* @date: 6/12/25
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*
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* **/
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module rom_sd(
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input logic clk,
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input logic reset,
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@ -28,34 +33,34 @@ logic buffer_half;
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// The ROM has 17 address bits and 8 data bits to store 128KiB, more than
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// enough for one second of 48khz audio
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xpm_memory_sprom #(
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.ADDR_WIDTH_A(17), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.ECC_BIT_RANGE("7:0"), // String
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.ECC_MODE("no_ecc"), // String
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.ECC_TYPE("none"), // String
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.IGNORE_INIT_SYNTH(0), // DECIMAL
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.ADDR_WIDTH_A(17), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.ECC_BIT_RANGE("7:0"), // String
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.ECC_MODE("no_ecc"), // String
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.ECC_TYPE("none"), // String
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.IGNORE_INIT_SYNTH(0), // DECIMAL
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.MEMORY_INIT_FILE("roundabout.mem"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_SIZE(131072*8), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.RAM_DECOMP("auto"), // String
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.READ_DATA_WIDTH_A(8), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_RESET_VALUE_A("0"), // String
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.RST_MODE_A("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.WAKEUP_TIME("disable_sleep") // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_SIZE(131072*8), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.RAM_DECOMP("auto"), // String
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.READ_DATA_WIDTH_A(8), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_RESET_VALUE_A("0"), // String
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.RST_MODE_A("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.WAKEUP_TIME("disable_sleep") // String
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)
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xpm_memory_sprom_inst (
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.douta(rom_data), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.addra(rom_addr), // ADDR_WIDTH_A-bit input: Address for port A read operations.
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.clka(clk), // 1-bit input: Clock signal for port A.
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.ena(rom_enable), // 1-bit input: Memory enable signal for port A. Must be high on clock
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.douta(rom_data), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.addra(rom_addr), // ADDR_WIDTH_A-bit input: Address for port A read operations.
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.clka(clk), // 1-bit input: Clock signal for port A.
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.ena(rom_enable), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read operations are initiated. Pipelined internally.
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.rsta(reset) // 1-bit input: Reset signal for the final port A output register stage.
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