diff --git a/design/sd/rom_sd.sv b/design/sd/rom_sd.sv
index 4c50175..82078e3 100644
--- a/design/sd/rom_sd.sv
+++ b/design/sd/rom_sd.sv
@@ -1,5 +1,10 @@
-// A dummy sdcard module for testing the audio port
-
+/****
+ * rom_sd.sv - reads audio data off a rom and feeds it to the audio buffer
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/25
+ *
+ * **/
 module rom_sd(
     input logic clk,
     input logic reset,
@@ -28,34 +33,34 @@ logic buffer_half;
 // The ROM has 17 address bits and 8 data bits to store 128KiB, more than
 // enough for one second of 48khz audio
 xpm_memory_sprom #(
-  .ADDR_WIDTH_A(17),              // DECIMAL
-  .AUTO_SLEEP_TIME(0),           // DECIMAL
-  .CASCADE_HEIGHT(0),            // DECIMAL
-  .ECC_BIT_RANGE("7:0"),         // String
-  .ECC_MODE("no_ecc"),           // String
-  .ECC_TYPE("none"),             // String
-  .IGNORE_INIT_SYNTH(0),         // DECIMAL
+  .ADDR_WIDTH_A(17),               // DECIMAL
+  .AUTO_SLEEP_TIME(0),             // DECIMAL
+  .CASCADE_HEIGHT(0),              // DECIMAL
+  .ECC_BIT_RANGE("7:0"),           // String
+  .ECC_MODE("no_ecc"),             // String
+  .ECC_TYPE("none"),               // String
+  .IGNORE_INIT_SYNTH(0),           // DECIMAL
   .MEMORY_INIT_FILE("roundabout.mem"),     // String
-  .MEMORY_INIT_PARAM("0"),       // String
-  .MEMORY_OPTIMIZATION("true"),  // String
-  .MEMORY_PRIMITIVE("auto"),     // String
-  .MEMORY_SIZE(131072*8),            // DECIMAL
-  .MESSAGE_CONTROL(0),           // DECIMAL
-  .RAM_DECOMP("auto"),           // String
-  .READ_DATA_WIDTH_A(8),        // DECIMAL
-  .READ_LATENCY_A(2),            // DECIMAL
-  .READ_RESET_VALUE_A("0"),      // String
-  .RST_MODE_A("SYNC"),           // String
-  .SIM_ASSERT_CHK(0),            // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-  .USE_MEM_INIT(1),              // DECIMAL
-  .USE_MEM_INIT_MMI(0),          // DECIMAL
-  .WAKEUP_TIME("disable_sleep")  // String
+  .MEMORY_INIT_PARAM("0"),         // String
+  .MEMORY_OPTIMIZATION("true"),    // String
+  .MEMORY_PRIMITIVE("auto"),       // String
+  .MEMORY_SIZE(131072*8),          // DECIMAL
+  .MESSAGE_CONTROL(0),             // DECIMAL
+  .RAM_DECOMP("auto"),             // String
+  .READ_DATA_WIDTH_A(8),           // DECIMAL
+  .READ_LATENCY_A(2),              // DECIMAL
+  .READ_RESET_VALUE_A("0"),        // String
+  .RST_MODE_A("SYNC"),             // String
+  .SIM_ASSERT_CHK(0),              // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .USE_MEM_INIT(1),                // DECIMAL
+  .USE_MEM_INIT_MMI(0),            // DECIMAL
+  .WAKEUP_TIME("disable_sleep")    // String
 )
 xpm_memory_sprom_inst (
-  .douta(rom_data),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
-  .addra(rom_addr),                   // ADDR_WIDTH_A-bit input: Address for port A read operations.
-  .clka(clk),                     // 1-bit input: Clock signal for port A.
-  .ena(rom_enable),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
+  .douta(rom_data),                // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
+  .addra(rom_addr),                // ADDR_WIDTH_A-bit input: Address for port A read operations.
+  .clka(clk),                      // 1-bit input: Clock signal for port A.
+  .ena(rom_enable),                // 1-bit input: Memory enable signal for port A. Must be high on clock
                                    // cycles when read operations are initiated. Pipelined internally.
 
   .rsta(reset)                     // 1-bit input: Reset signal for the final port A output register stage.