dilanthi
02e2d77640
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144 lines
4.5 KiB
Systemverilog
144 lines
4.5 KiB
Systemverilog
/****
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* rom_sd.sv - reads audio data off a rom and feeds it to the audio buffer
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*
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* @author: Dilanthi Prentice, Waylon Cude
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* @date: 6/12/25
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*
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* **/
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module rom_sd(
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input logic clk,
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input logic reset,
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output logic ready,
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buffer_interface.driver buffer
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);
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typedef enum logic [2:0]{
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RESET, DELAY, WRITEBUF, ENDWRITE, WAIT
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} state_t;
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state_t current, next;
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// First we write 2048B into the memory buffer, then signal to play it and
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// wait for half signal to avoid overwriting memory
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logic initializing;
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logic [16:0] rom_addr;
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logic [7:0] rom_data;
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logic rom_enable;
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logic buffer_half;
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// xpm_memory_sprom: Single Port ROM
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// Xilinx Parameterized Macro, version 2024.2
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// The ROM has 17 address bits and 8 data bits to store 128KiB, more than
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// enough for one second of 48khz audio
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xpm_memory_sprom #(
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.ADDR_WIDTH_A(17), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.ECC_BIT_RANGE("7:0"), // String
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.ECC_MODE("no_ecc"), // String
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.ECC_TYPE("none"), // String
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.IGNORE_INIT_SYNTH(0), // DECIMAL
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.MEMORY_INIT_FILE("roundabout.mem"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_SIZE(131072*8), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.RAM_DECOMP("auto"), // String
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.READ_DATA_WIDTH_A(8), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_RESET_VALUE_A("0"), // String
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.RST_MODE_A("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.WAKEUP_TIME("disable_sleep") // String
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)
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xpm_memory_sprom_inst (
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.douta(rom_data), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.addra(rom_addr), // ADDR_WIDTH_A-bit input: Address for port A read operations.
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.clka(clk), // 1-bit input: Clock signal for port A.
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.ena(rom_enable), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read operations are initiated. Pipelined internally.
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.rsta(reset) // 1-bit input: Reset signal for the final port A output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_A.
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);
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// End of xpm_memory_sprom_inst instantiation
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//next state logic
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always_comb
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begin
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case (current)
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RESET: if (reset) next = RESET;
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else next = DELAY;
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DELAY: next = WRITEBUF;
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WRITEBUF: if (buffer.addra < 1023) next = WRITEBUF;
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else if (buffer.addra == 1023) next = ENDWRITE;
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ENDWRITE: next = WAIT;
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WAIT: if (buffer_half == buffer.address_half) next = WAIT;
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else next = DELAY;
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default: next = RESET;
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endcase
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end
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//sequential output logic
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always_ff @(posedge clock)
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begin
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case (current)
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RESET: begin
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buffer_half <= 0;
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rom_addr <= 0;
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rom_enable <= 1;
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buffer.addra <= 0;
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ready <= 0;
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end
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DELAY: rom_addr <= rom_addr + 1;
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WRITEBUF: begin
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buffer.ena <= 1;
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buffer.dina <= rom_data;
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buffer.addra <= buffer.addra + 1;
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rom_addr <= rom_addr + 1;
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end
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ENDWRITE: begin
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buffer.ena <= 1;
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buffer.data <= rom_data;
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buffer.addra <= buffer.addra + 1;
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ready <= 1;
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end
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WAIT: buffer.ena <= 0;
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default: begin
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buffer_half <= 0;
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rom_addr <= 0;
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rom_enable <= 0;
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buffer.addra <= 0;
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buffer.dina <= 0;
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ready <= 0;
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end
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endcase
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end
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//sequential clocking block
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always_ff @(posedge clock)
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begin
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if (reset)
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current <= RESET;
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else
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current <= next;
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end
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endmodule
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