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How tf did it break bro
46 lines
924 B
Systemverilog
46 lines
924 B
Systemverilog
module sd_controller_tb;
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bit slow_clk,fast_clk,crc_clk;
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logic reset,sd_data;
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wire sd_cmd;
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wire ready;
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wire clk;
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audio_buffer_interface buffer ();
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sd_controller dut (.buffer(buffer.driver), .*);
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bit sd_write;
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assign sd_cmd = sd_write ? 'z : 0;
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initial forever #100 slow_clk = ~slow_clk;
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initial forever #1 crc_clk = ~crc_clk;
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initial forever #10 fast_clk = ~fast_clk;
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initial begin
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sd_write = 1;
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reset = 1;
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repeat (2) @(posedge slow_clk);
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reset = 0;
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repeat (200) @(posedge slow_clk);
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send_response();
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repeat (100) @(posedge slow_clk);
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send_response();
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repeat (100) @(posedge slow_clk);
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$finish;
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end
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task automatic send_response();
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for(int i=0;i<47;i++)
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@(posedge slow_clk) sd_write = 0;
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@(posedge slow_clk) sd_write = 1;
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endtask
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endmodule
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