module sd_controller_tb;
    bit slow_clk,fast_clk,crc_clk;
    logic reset,sd_data;
    wire sd_cmd;
    wire ready;
    wire clk;
    audio_buffer_interface buffer ();

    sd_controller dut (.buffer(buffer.driver), .*);

    bit sd_write;

    assign sd_cmd = sd_write ? 'z : 0;

    initial forever #100 slow_clk = ~slow_clk;

    initial forever #1 crc_clk = ~crc_clk;
    initial forever #10 fast_clk = ~fast_clk;

    initial begin

        sd_write = 1;
        reset = 1;
        repeat (2) @(posedge slow_clk);
        reset = 0;
        repeat (200) @(posedge slow_clk);
        send_response();

        repeat (100) @(posedge slow_clk);
        send_response();
        repeat (100) @(posedge slow_clk);

        $finish;

    end

    task automatic send_response();
        for(int i=0;i<47;i++)
            @(posedge slow_clk) sd_write = 0;
        @(posedge slow_clk) sd_write = 1;
    endtask



endmodule