Demo commit

The audio output is still messed up, but this commit gets everything as
ready as it can get. Fixed up all the testbenches and added state
machines for everything

verification/audio/audio_buffer_tb.sv

@@ -10,29 +10,22 @@ module audio_buffer_tb;
     logic play, stop;
     SPEED speed;
 
-    // Whether the current address being read from is in the upper or lower
-    // half of the 2KiB buffer
-    logic address_half;
-
     // Whether the audio buffer is currently playing
     logic playing;
 
     // A 16-bit audio sample to output
     logic [15:0] sample;
 
-    // Inputs for the memory buffer
-    logic [10:0] addra;
-    logic [7:0] dina;
-    logic clka, ena;
-
     logic [9:0] counter;
 
     logic [15:0] test_memory [1023:0];
-    audio_buffer dut(.*);
+
+    audio_buffer_interface buffer();
+    audio_buffer dut(.driver(buffer),.*);
 
     // The writer's clock should be much faster than the 48khz buffer clock
-    initial clka = 0;
-    always #5 clka = ~clka;
+    initial buffer.clka = 0;
+    always #5 buffer.clka = ~buffer.clka;
 
 
     // An order of magnitude difference is fine
@@ -83,38 +76,38 @@ module audio_buffer_tb;
         end
         // Writer
         begin
-            ena = 1;
+            buffer.ena = 1;
             for (int i = 0; i<= 1024; i++) begin
-                addra = i*2;
-                dina = i[7:0];
-                @(posedge clka)
-                addra = i*2+1;
-                dina = i[15:8];
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = i[7:0];
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = i[15:8];
+                @(posedge buffer.clka);
             end
-            wait (address_half==1);
+            wait (buffer.address_half==1);
             // random test, write to lower half of memory
             for (int i = 0; i< 512; i++) begin
-                addra = i*2;
-                dina = $urandom;
-                test_memory[i][7:0] = dina;
-                @(posedge clka)
-                addra = i*2+1;
-                dina = $urandom;
-                test_memory[i][15:8] = dina;
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = $urandom;
+                test_memory[i][7:0] = buffer.dina;
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = $urandom;
+                test_memory[i][15:8] = buffer.dina;
+                @(posedge buffer.clka);
             end
-            wait (address_half==0);
+            wait (buffer.address_half==0);
             // random test, write to upper half of memory
             for (int i = 512; i< 1024; i++) begin
-                addra = i*2;
-                dina = $urandom;
-                test_memory[i][7:0] = dina;
-                @(posedge clka)
-                addra = i*2+1;
-                dina = $urandom;
-                test_memory[i][15:8] = dina;
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = $urandom;
+                test_memory[i][7:0] = buffer.dina;
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = $urandom;
+                test_memory[i][15:8] = buffer.dina;
+                @(posedge buffer.clka);
             end
         end
         join

verification/audio/pwm_tb.sv

@@ -12,7 +12,7 @@ module pwm_tb;
     wire pwm_pin;
     logic [15:0] sample;
 
-    pwm dut (.*);
+    pwm #(16) dut (.*);
 
     initial forever #10 clk = ~clk;