Waylon Cude
f840d27b8e
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The audio output is still messed up, but this commit gets everything as ready as it can get. Fixed up all the testbenches and added state machines for everything
58 lines
1.3 KiB
Systemverilog
58 lines
1.3 KiB
Systemverilog
/*****
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* pwm_tb.sv - testbench for the pwm.sv module.
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*
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* @author: Dilanthi Prentice, Waylon Cude
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* @date: 6/12/2025
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* */
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module pwm_tb;
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bit clk, reset;
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logic load;
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wire pwm_pin;
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logic [15:0] sample;
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pwm #(16) dut (.*);
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initial forever #10 clk = ~clk;
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initial begin
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reset = 1;
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@(posedge clk);
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@(posedge clk);
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reset = 0;
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load = 1;
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sample = 0;
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for (int i=0; i < (1<<16)-1; i++) begin
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@(posedge clk) assert (pwm_pin === 0)
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else $error("Should be low at %d",i);
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end
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reset = 0;
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load = 1;
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sample = '1;
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@(posedge clk)
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for (int i=0; i < (1<<16)-1; i++) begin
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@(posedge clk) assert (pwm_pin === 'z)
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else $error("Should be high at %d",i);
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end
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reset = 0;
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load = 1;
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// Should be about half on
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sample = 1<<15;
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@(posedge clk)
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for (int i=0; i < (1<<15); i++) begin
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@(posedge clk) assert (pwm_pin === 'z)
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else $error("Should be high at %d",i);
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end
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sample = 1<<15;
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for (int i = (1 << 15); i < (1<<16)-1; i++) begin
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@(posedge clk) assert (pwm_pin === 0)
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else $error("Should be low at %d",i);
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end
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$finish;
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end
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endmodule
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