Demo commit

The audio output is still messed up, but this commit gets everything as
ready as it can get. Fixed up all the testbenches and added state
machines for everything

verification/audio/audio_buffer_tb.sv

@@ -10,29 +10,22 @@ module audio_buffer_tb;
     logic play, stop;
     SPEED speed;
 
-    // Whether the current address being read from is in the upper or lower
-    // half of the 2KiB buffer
-    logic address_half;
-
     // Whether the audio buffer is currently playing
     logic playing;
 
     // A 16-bit audio sample to output
     logic [15:0] sample;
 
-    // Inputs for the memory buffer
-    logic [10:0] addra;
-    logic [7:0] dina;
-    logic clka, ena;
-
     logic [9:0] counter;
 
     logic [15:0] test_memory [1023:0];
-    audio_buffer dut(.*);
+
+    audio_buffer_interface buffer();
+    audio_buffer dut(.driver(buffer),.*);
 
     // The writer's clock should be much faster than the 48khz buffer clock
-    initial clka = 0;
-    always #5 clka = ~clka;
+    initial buffer.clka = 0;
+    always #5 buffer.clka = ~buffer.clka;
 
 
     // An order of magnitude difference is fine
@@ -83,38 +76,38 @@ module audio_buffer_tb;
         end
         // Writer
         begin
-            ena = 1;
+            buffer.ena = 1;
             for (int i = 0; i<= 1024; i++) begin
-                addra = i*2;
-                dina = i[7:0];
-                @(posedge clka)
-                addra = i*2+1;
-                dina = i[15:8];
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = i[7:0];
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = i[15:8];
+                @(posedge buffer.clka);
             end
-            wait (address_half==1);
+            wait (buffer.address_half==1);
             // random test, write to lower half of memory
             for (int i = 0; i< 512; i++) begin
-                addra = i*2;
-                dina = $urandom;
-                test_memory[i][7:0] = dina;
-                @(posedge clka)
-                addra = i*2+1;
-                dina = $urandom;
-                test_memory[i][15:8] = dina;
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = $urandom;
+                test_memory[i][7:0] = buffer.dina;
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = $urandom;
+                test_memory[i][15:8] = buffer.dina;
+                @(posedge buffer.clka);
             end
-            wait (address_half==0);
+            wait (buffer.address_half==0);
             // random test, write to upper half of memory
             for (int i = 512; i< 1024; i++) begin
-                addra = i*2;
-                dina = $urandom;
-                test_memory[i][7:0] = dina;
-                @(posedge clka)
-                addra = i*2+1;
-                dina = $urandom;
-                test_memory[i][15:8] = dina;
-                @(posedge clka);
+                buffer.addra = i*2;
+                buffer.dina = $urandom;
+                test_memory[i][7:0] = buffer.dina;
+                @(posedge buffer.clka)
+                buffer.addra = i*2+1;
+                buffer.dina = $urandom;
+                test_memory[i][15:8] = buffer.dina;
+                @(posedge buffer.clka);
             end
         end
         join

verification/audio/pwm_tb.sv

@@ -12,7 +12,7 @@ module pwm_tb;
     wire pwm_pin;
     logic [15:0] sample;
 
-    pwm dut (.*);
+    pwm #(16) dut (.*);
 
     initial forever #10 clk = ~clk;
 

verification/debouncer_tb.sv

@@ -60,6 +60,9 @@ initial begin
         errors++;
     end
 
+    @(posedge clk);
+    @(posedge clk);
+
     $display("Generating random input to test assertions");
     for (int i=0; i<TESTCYCLES; i++) begin
         source = $urandom;

verification/sd/read_data_tb.sv

@@ -16,7 +16,7 @@ module read_data_tb;
     // A 16-bit audio sample to output
     logic [15:0] sample;
 
-    logic sd_data;
+    logic [3:0] sd_data;
 
     audio_buffer_interface bufferInterface(); 
 
@@ -104,37 +104,41 @@ module read_data_tb;
     end
     task automatic write_random_sd(int start);
         @(posedge sd_clk);
-        sd_data = 1;
+        sd_data = '1;
         // send start bit
         @(posedge sd_clk);
         // send 256 data bits
         sd_data = 0;
         for (int i = 0; i < 256; i++) begin
-            write_byte(test_memory[start+i][7:0]);
-            write_byte(test_memory[start+i][15:8]);
+            write_byte(test_memory[start-i-1][7:0]);
+            write_byte(test_memory[start-i-1][15:8]);
         end
         // Simulate randomized crc bits and stop bit
-        repeat (16) @(posedge sd_clk) sd_data=$urandom;
-        @(posedge sd_clk) sd_data=1;
+        repeat (16*4) @(posedge sd_clk) sd_data=$urandom;
+        @(posedge sd_clk) sd_data='1;
     endtask
     task automatic write_linear_sd(int start);
         @(posedge sd_clk);
-        sd_data = 1;
+        sd_data = '1;
         // send start bit
         @(posedge sd_clk);
         // send 256 data bits
         sd_data = 0;
+        start += 256;
         for (int i = 0; i < 256; i++) begin
+            // NOTE: These are in the wrong order??
+            //       One of the weird cases where simulation is different
+            //       than hardware
             write_byte(start[7:0]);
             write_byte(start[15:8]);
-            start = start+1;
+            start = start-1;
         end
         // Simulate crc bits and stop bit
-        repeat (17) @(posedge sd_clk) sd_data=1;
+        repeat (16*4+1) @(posedge sd_clk) sd_data='1;
     endtask
     task automatic write_byte(logic [7:0] b);
-        for (int i=0; i<8; i++)
-            @(posedge sd_clk) sd_data=b[7-i];
+        @(posedge sd_clk) sd_data=b[7:4];
+        @(posedge sd_clk) sd_data=b[3:0];
     endtask
 
 endmodule

verification/sd/send_command_tb.sv

@@ -40,6 +40,7 @@ initial begin
     counter = 48;
 
     @(posedge clk);
+    start = 0;
 
     // Try receiving the CMD8
     while (counter != 0) begin
@@ -54,9 +55,11 @@ initial begin
     assert (fill_me === {2'b01, 6'd8, 32'h1AA, 8'h87})
         else $error("Received wrong command, got 0x%x",fill_me);
 
+    repeat (1) @(posedge clk);
     assert (ready)
         else $error("SD command sender not ready");
 
+    repeat (10) @(posedge clk);
 
     $finish;
 end

verification/segment_display/seconds_display_tb.sv

@@ -16,7 +16,7 @@ wire [6:0] display_ones;
 logic [6:0] expected_tens;
 logic [6:0] expected_ones;
 
-seconds_display Dut(.*);
+sixty_display Dut(.number(seconds),.*);
 initial begin
     $display("Testing seconds_display");
     for (seconds=0; seconds<60; seconds++) begin