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Added playback controller and testbench
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This commit is contained in:
dilanthi 2025-05-22 20:06:31 -07:00
parent 18aab51325
commit 3f626074f9
4 changed files with 515 additions and 318 deletions
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62
SDVD.xpr
View File

@ -4,7 +4,7 @@
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="68" Path="/home/uelen/Sync/ece571/SDVD/SDVD.xpr">
<Project Product="Vivado" Version="7" Minor="68" Path="C:/Users/midni/OneDrive/Desktop/SDVD/SDVD.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ef9705cecf4b4a4599c24f6838c9c6ea"/>
@ -43,9 +43,8 @@
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="BoardPart" Val="digilentinc.com:nexys-a7-100t:part0:1.2"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../.Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="playback_controller_tb"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
@ -61,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="nexys-a7-100t"/>
<Option Name="WTXSimLaunchSim" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="22"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -199,6 +198,7 @@
</Config>
</FileSet>
<FileSet Name="seconds_display_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/seconds_display_tb" RelGenDir="$PGENDIR/seconds_display_tb">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/verification/segment_display/seconds_display_tb.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -223,6 +223,39 @@
<Option Name="CosimElf" Val=""/>
</Config>
</FileSet>
<FileSet Name="playback_controller_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/playback_controller_tb" RelGenDir="$PGENDIR/playback_controller_tb">
<File Path="$PPRDIR/design/sdvd_defs.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/verification/playback_controller_tb.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="playback_controller_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="VerilogDir" Val="$PPRDIR/design"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="CosimPdi" Val=""/>
<Option Name="CosimPlatform" Val=""/>
<Option Name="CosimElf" Val=""/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@ -235,30 +268,26 @@
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
@ -273,15 +302,12 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">

69
design/playback_controller.sv
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@ -14,10 +14,79 @@ module playback_controller(
output SPEED speed
);
typedef enum logic [2:0] {
PAUSE, PLAY, FF2, FF4, FF8
} state_t;
state_t current, next;
wire play_pulse,ff_pulse;
// NOTE: These might need to be hooked to an even lower clock? Not sure
debouncer playDebouncer (clk,reset,play,play_pulse);
debouncer ffDebouncer (clk,reset,ff,ff_pulse);
//next state logic
always_comb
begin
unique case (current)
PAUSE:
begin
if (play_pulse) next = PLAY;
else if (ff_pulse) next = FF2;
else next = PAUSE;
end
PLAY:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF2;
else next = PLAY;
end
FF2:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF4;
else next = FF2;
end
FF4:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF8;
else next = FF4;
end
FF8:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF8;
else next = FF8;
end
default:
next = PAUSE;
endcase
end
//output logic
always_comb
begin
unique case (current)
PAUSE: speed = 0;
PLAY: speed = 1;
FF2: speed = 2;
FF4: speed = 4;
FF8: speed = 8;
default:speed = 0;
endcase
end
//sequential logic
always_ff @(posedge clk)
begin
if (reset)
current <= PAUSE;
else
current <= next;
end
endmodule

4
verification/debouncer_tb.sv
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@ -56,8 +56,4 @@ initial begin
$finish;
end
endmodule

106
verification/playback_controller_tb.sv Normal file
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@ -0,0 +1,106 @@
/****
* playback_controller_tb.sv - a testbench for the playback_controller.sv
* module.
*
* @author: Dilanthi Prentice
* @date: [unsure of due date]
*
* */
`include "sdvd_defs.sv"
import sdvd_defs::SPEED;
module playback_controller_tb;
logic clk, reset;
logic play, ff;
SPEED speed;
int errors;
//instatiate the dut
playback_controller dut(clk, reset, play, ff, speed);
//clock generation
initial clk = 0;
always #5 clk = ~clk;
//play button press
task press_play();
play = 1;
@(posedge clk);
play = 0;
@(posedge clk);
endtask
//ff button press
task press_ff();
ff = 1;
@(posedge clk);
ff = 0;
@(posedge clk);
endtask
initial
begin
@(posedge clk);
play = 0;
ff = 0;
reset = 1;
@(posedge clk);
reset = 0;
@(posedge clk);
assert (speed === 0) else
begin
$error("Speed not zero after reset");
errors++;
end
@(posedge clk);
press_play();
assert (speed === 1) else
begin
$error("Play not working");
errors++;
end
press_play();
assert (speed === 0) else
begin
$error("Pause not working");
errors++;
end
press_ff();
assert (speed === 2) else
begin
$error("Not in FF2 after ff btn pressed once");
errors++;
end
press_ff();
assert (speed === 4) else
begin
$error("Not in FF4 after ff btn pressed twice");
errors++;
end
press_ff();
assert (speed === 8) else
begin
$error("Not in FF8 after ff btn pressed thrice");
errors++;
end
press_play();
assert (speed === 0) else
begin
$error("Unsuccessful return to pause after play btn pressed from a FF state");
errors++;
end
if (errors === 0)
$display("No errors detected in playback_controller");
$finish;
end
endmodule