dilanthi
d4bedd06ce
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added x16 fast forward speed to playback_controller.sv corrected dates on pwn.sv, playback_controller.sv, display_converter.sv, and seconds_display.sv
111 lines
2.5 KiB
Systemverilog
111 lines
2.5 KiB
Systemverilog
/*****
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* playback_controller.sv - A finite state machine with states that control
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* playback speed. In additon to playing and pausing
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* it can fast forward at 2x speed, 4x speed, 8x
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* speed and 16x speed.
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*
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* @author: Dilanthi Prentice, Waylon Cude
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* @date: 6/12/25
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*
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* */
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`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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module playback_controller(
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// This clock should be reasonably slow
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input logic clk,
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input logic reset,
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// Play and pause are the same button
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input logic play,
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input logic ff,
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// Output is 0, 1x, 2x, 4x, 8x or 16x
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output SPEED speed
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);
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typedef enum logic [2:0] {
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PAUSE, PLAY, FF2, FF4, FF8, FF16
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} state_t;
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state_t current, next;
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wire play_pulse,ff_pulse;
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// NOTE: These might need to be hooked to an even lower clock? Not sure
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debouncer playDebouncer (clk,reset,play,play_pulse);
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debouncer ffDebouncer (clk,reset,ff,ff_pulse);
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//next state logic
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always_comb
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begin
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unique case (current)
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PAUSE:
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begin
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if (play_pulse) next = PLAY;
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else if (ff_pulse) next = FF2;
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else next = PAUSE;
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end
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PLAY:
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begin
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if (play_pulse) next = PAUSE;
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else if (ff_pulse) next = FF2;
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else next = PLAY;
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end
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FF2:
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begin
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if (play_pulse) next = PAUSE;
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else if (ff_pulse) next = FF4;
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else next = FF2;
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end
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FF4:
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begin
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if (play_pulse) next = PAUSE;
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else if (ff_pulse) next = FF8;
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else next = FF4;
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end
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FF8:
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begin
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if (play_pulse) next = PAUSE;
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else if (ff_pulse) next = FF16;
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else next = FF8;
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end
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FF16:
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begin
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if (play_pulse) next = PAUSE;
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else if (ff_pulse) next = FF16;
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else next = FF16;
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end
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default:
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next = PAUSE;
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endcase
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end
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//output logic
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always_comb
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begin
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unique case (current)
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PAUSE: speed = 0;
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PLAY: speed = 1;
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FF2: speed = 2;
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FF4: speed = 4;
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FF8: speed = 8;
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FF16: speed = 16;
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default:speed = 0;
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endcase
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end
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//sequential logic
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always_ff @(posedge clk)
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begin
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if (reset)
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current <= PAUSE;
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else
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current <= next;
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end
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endmodule
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