Waylon Cude
fe227d1b61
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How tf did it break bro
32 lines
685 B
Systemverilog
32 lines
685 B
Systemverilog
module modular_clock_gen(
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input clk, reset,
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output logic oclk
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);
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parameter DIVISOR;
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logic [$clog2(DIVISOR)-1:0] counter;
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logic set;
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// clock will be high for about half of the cycle, depending on integer
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// rounding
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// OOPS this makes it combinational
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//assign oclk = counter < (DIVISOR/2);
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always_ff @(posedge clk) begin
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// modular clock has to keep ticking through reset
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// so everything with a synchronous reset actually works
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if (reset && !set) begin
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counter <= DIVISOR-1;
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set <= 1;
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end
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else if (counter == 0)
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counter <= DIVISOR-1;
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else
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counter <= counter - 1;
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oclk <= counter < (DIVISOR/2);
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end
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endmodule
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