68 lines
1.8 KiB
Systemverilog
68 lines
1.8 KiB
Systemverilog
/****
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* low_freq_clock_gen.sv - Generates different clock frequencies to drive
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* different state machines and different parts of
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* the design.
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*
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* @author: Waylon Cude, Dilanthi Prentice
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* @date: 6/12/2025
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* */
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`ifdef VERILATOR
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`include "sdvd_defs.sv"
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`endif
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import sdvd_defs::SPEED;
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// Takes in a 100MHz clock and generates the very low freq signals needed
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// for driving the control logic
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module low_freq_clock_gen(
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input logic clk, reset,
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input SPEED speed,
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output logic clk1k, clk10h, seconds_pulse
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);
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// Hardcoded to be 1,000,000/4,000
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// Relying on constant maths makes it the wrong size
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localparam num_cycles = 25_000;
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logic [$clog2(num_cycles):0] counter;
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logic [$clog2(4000):0] seconds_counter;
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logic [$clog2(4000):0] clock_divider_counter;
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always_ff @(posedge clk) begin
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if (reset) begin
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counter <= num_cycles;
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clk1k <= 0;
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clk10h <= 0;
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seconds_pulse <= 0;
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seconds_counter <= 0;
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clock_divider_counter <= 0;
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end
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// At 4khz increment the seconds counter and output clocks
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else if (counter == 0) begin
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counter <= num_cycles;
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seconds_counter <= seconds_counter + {9'b0, speed};
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clock_divider_counter <= clock_divider_counter + 1;
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if (seconds_counter >= 4000) begin
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seconds_counter <= seconds_counter-4000;
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// Should we flop it or pulse at 100MHz?
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seconds_pulse <= 1;
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end
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else
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seconds_pulse <= 0;
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if (clock_divider_counter == 4000)
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clock_divider_counter <= 0;
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// Generate output clocks
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if (clock_divider_counter % 4 == 0)
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clk1k <= ~clk1k;
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if (clock_divider_counter % 400 == 0)
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clk10h <= ~clk10h;
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end
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else
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counter <= counter - 1;
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end
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endmodule
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