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This adds some unnecessary stuff into the debug core that I used to troubleshoot. There are like 5 bugfixes here. Especially of note is the low freq clock gen, I was trying to use modulo like you would do in a computer program but it was too slow, so I had to move the logic around a bunch.
21 lines
539 B
Systemverilog
21 lines
539 B
Systemverilog
// NOTE: This expects to be driven with a 100khz clock
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module display_anode_driver(
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input logic clk,
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input logic reset,
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output logic [7:0] AN,
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output logic [2:0] mux_select);
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// This is just a shift register that drives each anode individually
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always_ff @(posedge clk) begin
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if (reset) begin
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AN <= '1 - 1;
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mux_select <= 0;
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end
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else begin
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AN <= {AN[6:0], AN[7]};
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// Letting this overflow will automatically reset it
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mux_select <= mux_select + 1;
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end
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end
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endmodule
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