SDVD/design/playback_controller.sv
dilanthi 3f626074f9
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Added playback controller and testbench
2025-05-22 20:06:31 -07:00

93 lines
1.9 KiB
Systemverilog

`include "sdvd_defs.sv"
import sdvd_defs::SPEED;
module playback_controller(
// This clock should be reasonably slow
input logic clk,
input logic reset,
// Play and pause are the same button
input logic play,
input logic ff,
// Output is 0, 1x, 2x, 4x, or 8x
output SPEED speed
);
typedef enum logic [2:0] {
PAUSE, PLAY, FF2, FF4, FF8
} state_t;
state_t current, next;
wire play_pulse,ff_pulse;
// NOTE: These might need to be hooked to an even lower clock? Not sure
debouncer playDebouncer (clk,reset,play,play_pulse);
debouncer ffDebouncer (clk,reset,ff,ff_pulse);
//next state logic
always_comb
begin
unique case (current)
PAUSE:
begin
if (play_pulse) next = PLAY;
else if (ff_pulse) next = FF2;
else next = PAUSE;
end
PLAY:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF2;
else next = PLAY;
end
FF2:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF4;
else next = FF2;
end
FF4:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF8;
else next = FF4;
end
FF8:
begin
if (play_pulse) next = PAUSE;
else if (ff_pulse) next = FF8;
else next = FF8;
end
default:
next = PAUSE;
endcase
end
//output logic
always_comb
begin
unique case (current)
PAUSE: speed = 0;
PLAY: speed = 1;
FF2: speed = 2;
FF4: speed = 4;
FF8: speed = 8;
default:speed = 0;
endcase
end
//sequential logic
always_ff @(posedge clk)
begin
if (reset)
current <= PAUSE;
else
current <= next;
end
endmodule