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This adds some unnecessary stuff into the debug core that I used to troubleshoot. There are like 5 bugfixes here. Especially of note is the low freq clock gen, I was trying to use modulo like you would do in a computer program but it was too slow, so I had to move the logic around a bunch.
8 lines
92 B
Systemverilog
8 lines
92 B
Systemverilog
//this interfaces with block ram
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module audio_buffer(
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input logic clk, reset,
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);
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