uelen 423f89a665 Commit the project file again ...

Oops, forgot to do this after adding a file

2025-05-16 19:27:02 -07:00

.woodpecker

Add a wowrkflow to test that everything works

2025-05-07 17:40:55 -07:00

design

Add some stubbed out modules for the first bit

2025-05-16 17:58:25 -07:00

verification

Add empty debouncer tb

2025-05-16 18:53:05 -07:00

.gitignore

Add vivado project

2025-05-16 17:16:08 -07:00

modules.md

Initial commit

2025-05-06 13:46:53 -07:00

Nexys-A7-100T-Master.xdc

Add vivado project

2025-05-16 17:16:08 -07:00

SDVD.xpr

Commit the project file again

2025-05-16 19:27:02 -07:00

S

Description

An FPGA video player

353 MiB

Languages

SystemVerilog 73.3%

Tcl 26.6%

Python 0.1%