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Also fixed up the one type I found in the seconds display
12 lines
331 B
Systemverilog
12 lines
331 B
Systemverilog
// NOTE: This expects to be driven with a 100khz clock
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module display_anode_driver(input logic clk, input logic reset, output logic [7:0] AN);
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// This is just a shift register that drives each anode individually
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always_ff @(posedge clk) begin
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if (reset)
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AN <= 1;
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else
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AN <= {AN[6:0], AN[7]};
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end
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endmodule
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