// NOTE: This expects to be driven with a 100khz clock
module display_anode_driver(input logic clk, input logic reset, output logic [7:0] AN);

// This is just a shift register that drives each anode individually
always_ff @(posedge clk) begin
    if (reset)
        AN <= 1;
    else
        AN <= {AN[6:0], AN[7]};
end
endmodule