Waylon Cude
2fde75a330
Some of this stuff should get split out into 7-segment logic probably, having logic in the top file seems like a bad call
46 lines
1.3 KiB
Systemverilog
46 lines
1.3 KiB
Systemverilog
`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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// Takes in a 100MHz clock and generates the very low freq signals needed
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// for driving the control logic
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module low_freq_clock_gen(
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input logic clk, reset,
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input SPEED speed,
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output logic clk1k, clk10h, seconds_pulse
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);
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logic [$clog2(100_000_000):0] counter;
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logic [$clog2(4000):0] seconds_counter;
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logic clk4k;
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assign clk1k = (counter % (100_000_000/1000)) != 0;
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assign clk10h = (counter % (100_000_000/10)) != 0;
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assign clk4k = (counter % (100_000_000/4000)) != 0;
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always_ff @(posedge clk) begin
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// NOTE: This generates a pulse on the same clock cycle that reset is
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// asserted. Is that bad??
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if (reset)
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counter <= 0;
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// Roll the counter over back to zero every second
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else if (counter == 99_999_999)
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counter <= 0;
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else
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counter <= counter + 1;
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// This logic handles the variable-speed seconds counter
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if (reset) begin
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seconds_pulse <= 0;
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seconds_counter <= 0;
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end
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else if (clk4k && seconds_counter >= 4000) begin
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seconds_counter <= seconds_counter-4000;
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seconds_pulse <= 1;
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end
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else if (clk4k) begin
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seconds_pulse <= 0;
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seconds_counter <= seconds_counter + {9'b0, speed};
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end
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end
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endmodule
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