Waylon Cude
f840d27b8e
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The audio output is still messed up, but this commit gets everything as ready as it can get. Fixed up all the testbenches and added state machines for everything
118 lines
3.6 KiB
Systemverilog
118 lines
3.6 KiB
Systemverilog
`ifdef VERILATOR
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`include "sdvd_defs.sv"
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`endif
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import sdvd_defs::SPEED;
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module audio_buffer_tb;
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logic clk, reset;
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// Control signals
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logic play, stop;
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SPEED speed;
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// Whether the audio buffer is currently playing
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logic playing;
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// A 16-bit audio sample to output
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logic [15:0] sample;
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logic [9:0] counter;
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logic [15:0] test_memory [1023:0];
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audio_buffer_interface buffer();
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audio_buffer dut(.driver(buffer),.*);
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// The writer's clock should be much faster than the 48khz buffer clock
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initial buffer.clka = 0;
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always #5 buffer.clka = ~buffer.clka;
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// An order of magnitude difference is fine
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initial clk = 0;
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always #50 clk = ~clk;
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// Reader
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initial begin
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`ifdef DEBUG
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$monitor("PLAYING: %b ADDR: 0x%x DATA: 0x%x WILLDELAY: %b",
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playing, dut.address, dut.doutb,dut.delay);
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`endif
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fork
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//Reader
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begin
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play = 0;
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stop = 0;
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clk = 0;
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reset = 0;
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speed = 1;
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@(posedge clk)
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reset = 1;
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@(posedge clk)
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reset = 0;
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play = 1;
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@(posedge clk)
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assert (playing == 1) else $error("Audio buffer not playing");
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// Wait an extra clock cycle because of the blockmem delay
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@(posedge clk)
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// The most basic test we can do here is an incrementing counter,
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// where the stored sample is the same as the address
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$display("Running linear test");
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for (counter = 0; counter != 1023; counter++) begin
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#1
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assert ({6'b0, counter} === sample) else
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$error("Invalid sample, expected 0x%x but found 0x%x",counter,sample);
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@(posedge clk);
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end
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@(posedge clk);
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$display("Running randomized test");
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for (counter = 0; counter != 1023; counter++) begin
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#1
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assert (test_memory[counter] === sample) else
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$error("Invalid sample, expected 0x%x but found 0x%x",test_memory[counter],sample);
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@(posedge clk);
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end
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end
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// Writer
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begin
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buffer.ena = 1;
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for (int i = 0; i<= 1024; i++) begin
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buffer.addra = i*2;
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buffer.dina = i[7:0];
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@(posedge buffer.clka)
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buffer.addra = i*2+1;
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buffer.dina = i[15:8];
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@(posedge buffer.clka);
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end
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wait (buffer.address_half==1);
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// random test, write to lower half of memory
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for (int i = 0; i< 512; i++) begin
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buffer.addra = i*2;
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buffer.dina = $urandom;
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test_memory[i][7:0] = buffer.dina;
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@(posedge buffer.clka)
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buffer.addra = i*2+1;
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buffer.dina = $urandom;
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test_memory[i][15:8] = buffer.dina;
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@(posedge buffer.clka);
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end
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wait (buffer.address_half==0);
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// random test, write to upper half of memory
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for (int i = 512; i< 1024; i++) begin
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buffer.addra = i*2;
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buffer.dina = $urandom;
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test_memory[i][7:0] = buffer.dina;
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@(posedge buffer.clka)
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buffer.addra = i*2+1;
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buffer.dina = $urandom;
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test_memory[i][15:8] = buffer.dina;
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@(posedge buffer.clka);
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end
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end
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join
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$finish;
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end
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endmodule
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