Waylon Cude
f840d27b8e
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The audio output is still messed up, but this commit gets everything as ready as it can get. Fixed up all the testbenches and added state machines for everything
56 lines
1.1 KiB
Systemverilog
56 lines
1.1 KiB
Systemverilog
/****
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* pwm.sv - drives the pwm audio output on the FPGA given a single 16-bit
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* sample.
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*
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* @author: Dilanthi Prentice, Waylon Cude
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* @date: 6-12-2025
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*
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*
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* */
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module pwm(
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input logic clk, reset,
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// Load control signal, if this is high we should load a new sample
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input logic load,
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// The audio sample to play back
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input logic [15:0] sample,
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// The audio output pin
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output wire pwm_pin
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);
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// This can't be 16 or we are slowing the audio rate down by a factor of
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// 2^5=32
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parameter DEPTH=11;
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logic [DEPTH-1:0] pulse_counter;
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(* MARK_DEBUG = "TRUE" *)
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logic [15:0] sample_buffer;
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logic should_output;
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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pulse_counter <= 0;
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sample_buffer <= 0;
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should_output <= 0;
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end
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else
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begin
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if (load)
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sample_buffer <= sample;
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pulse_counter <= pulse_counter + 1;
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if (pulse_counter < sample_buffer[15-:DEPTH])
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should_output <= 1;
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else
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should_output <= 0;
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end
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end
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assign pwm_pin = should_output ? 'z : '0;
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endmodule
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