uelen/SDVD
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34d62a197fefd763b4c94b51a8c96b42fe82dcbc
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uelen 34d62a197f
ci/woodpecker/push/test-workflow Pipeline was successful
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Add some stubbed out modules for the first bit 
Hopefully theses are right ...
2025-05-16 17:58:25 -07:00
.woodpecker
Add a wowrkflow to test that everything works
2025-05-07 17:40:55 -07:00
design
Add some stubbed out modules for the first bit
2025-05-16 17:58:25 -07:00
verification
Initial commit
2025-05-06 13:46:53 -07:00
.gitignore
Add vivado project
2025-05-16 17:16:08 -07:00
modules.md
Initial commit
2025-05-06 13:46:53 -07:00
Nexys-A7-100T-Master.xdc
Add vivado project
2025-05-16 17:16:08 -07:00
SDVD.xpr
Add some stubbed out modules for the first bit
2025-05-16 17:58:25 -07:00
S
Description
An FPGA video player
353 MiB
Languages
SystemVerilog 73.3%
Tcl 26.6%
Python 0.1%