Waylon Cude
da7d026d06
NOTE: This doesn't actually compile yet, but it should once changes to the seconds display are pushed
52 lines
1.3 KiB
Systemverilog
52 lines
1.3 KiB
Systemverilog
module seconds_display_tb;
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int errors = 0;
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logic [5:0] seconds;
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wire [6:0] display_tens;
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wire [6:0] display_ones;
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logic [6:0] expected_tens;
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logic [6:0] expected_ones;
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seconds_display Dut(.*);
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initial begin
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$display("Testing seconds_display");
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for (seconds=0; seconds<60; seconds++) begin
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expected_ones = encode_number(seconds % 10);
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expected_tens = encode_number(seconds /10);
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#1
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if (display_ones !== expected_ones) begin
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errors++;
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$display("Failed ones test case, displayed = %b, expected = %b",
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display_ones,
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expected_ones);
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end
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else
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if (display_tens !== expected_tens) begin
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errors++;
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$display("Failed tens test case, displayed = %b, expected = %b",
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display_tens,
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expected_tens);
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end
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end
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if (errors == 0)
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$display("All tests passing");
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end
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endmodule
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function automatic logic [6:0] encode_number(logic [5:0] num);
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case (num)
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0: return 7'b1111110;
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1: return 7'b0000110;
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2: return 7'b1101101;
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3: return 7'b1111001;
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4: return 7'b0110011;
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5: return 7'b1011011;
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6: return 7'b1011111;
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7: return 7'b1110000;
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8: return 7'b1111111;
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9: return 7'b1111011;
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endcase
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endfunction
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