All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
Hopefully theses are right ...
11 lines
182 B
Systemverilog
11 lines
182 B
Systemverilog
module seconds_display(
|
|
input logic clk,
|
|
input logic reset,
|
|
input [$clog2(60)-1:0] counter,
|
|
output [7:0] display_tens,
|
|
output [7:0] display_ones
|
|
);
|
|
|
|
|
|
endmodule
|