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64 lines
1.1 KiB
Systemverilog
64 lines
1.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module debouncer_tb;
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logic clk,reset,source;
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wire out;
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int errors;
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debouncer Dut (.*);
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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initial begin
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$display("Testing debouncer");
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reset = 1;
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source = 0;
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@(posedge clk);
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@(posedge clk);
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reset = 0;
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@(posedge clk);
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source = 1;
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#1;
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assert (out == 1) else begin
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$error("Output not brought high during first press");
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errors++;
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end
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@(posedge clk);
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#1;
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assert (out == 0) else begin
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$error("Output not brought low after first press");
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errors++;
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end
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@(posedge clk);
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source = 0;
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@(posedge clk);
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source = 1;
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#1;
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assert (out == 1) else begin
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$error("Output not brought high during second press");
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errors++;
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end
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source = 0;
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@(posedge clk);
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#1;
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assert (out == 0) else begin
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$error("Output not brought low after second press");
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errors++;
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end
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if (errors == 0)
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$display("Found no errors while testing debouncer");
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$finish;
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end
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endmodule
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