Waylon Cude
71f08bdf15
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Works great according to the testbench
50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
module crc_gen_tb;
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parameter CRCBITS=7;
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parameter COMMANDLEN=40;
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parameter POLYNOMIAL='h89;
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logic clk, reset, start, ready;
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logic [COMMANDLEN-1:0] num;
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logic [CRCBITS-1:0] crc;
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logic [CRCBITS-1:0] test_cases [logic [COMMANDLEN-1:0]];
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crc_gen #(CRCBITS,COMMANDLEN,POLYNOMIAL) dut (.*);
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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initial begin
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test_cases = '{
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'h1234567890: 'h10,
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'hBEEFB05535: 'h05,
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'h5544992211: 'h17,
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'0: '0
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};
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reset = 1;
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start = 0;
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repeat (2) @(posedge clk);
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reset = 0;
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@(posedge clk);
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foreach (test_cases[key]) begin
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wait (ready);
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num = key;
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@(posedge clk);
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start = 1;
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@(posedge clk);
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start = 0;
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@(posedge clk);
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wait(ready);
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assert (crc === test_cases[key])
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else $error("Invalid crc, found 0x%x but expected 0x%x",crc,test_cases[key]);
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end
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$finish;
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end
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endmodule
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