Nexys-A7-100T-Master.xdc

@@ -249,8 +249,8 @@ set_property port_width 16 [get_debug_ports u_ila_0/probe4]
 connect_debug_port u_ila_0/probe4 [get_nets [list {audioOutput/sample_buffer[0]} {audioOutput/sample_buffer[1]} {audioOutput/sample_buffer[2]} {audioOutput/sample_buffer[3]} {audioOutput/sample_buffer[4]} {audioOutput/sample_buffer[5]} {audioOutput/sample_buffer[6]} {audioOutput/sample_buffer[7]} {audioOutput/sample_buffer[8]} {audioOutput/sample_buffer[9]} {audioOutput/sample_buffer[10]} {audioOutput/sample_buffer[11]} {audioOutput/sample_buffer[12]} {audioOutput/sample_buffer[13]} {audioOutput/sample_buffer[14]} {audioOutput/sample_buffer[15]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 10 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {audioBuffer/address[0]} {audioBuffer/address[1]} {audioBuffer/address[2]} {audioBuffer/address[3]} {audioBuffer/address[4]} {audioBuffer/address[5]} {audioBuffer/address[6]} {audioBuffer/address[7]} {audioBuffer/address[8]} {audioBuffer/address[9]}]]
+set_property port_width 11 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {audioBuffer/address[0]} {audioBuffer/address[1]} {audioBuffer/address[2]} {audioBuffer/address[3]} {audioBuffer/address[4]} {audioBuffer/address[5]} {audioBuffer/address[6]} {audioBuffer/address[7]} {audioBuffer/address[8]} {audioBuffer/address[9]} {audioBuffer/address[10]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
 set_property port_width 1 [get_debug_ports u_ila_0/probe6]

SDVD.xpr

@@ -664,7 +664,7 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
         <Step Id="init_design"/>
@@ -677,7 +677,6 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
       <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>

design/nexys_a7_top.sv

@@ -130,7 +130,6 @@ playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
         clk_100khz,
         clk_25mhz,
         CLK100MHZ,
-        clk_1mhz,
         reset,
         SD_DAT,
         SD_CMD,
@@ -139,7 +138,7 @@ playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
         audio_interface.driver
     );
 
-    audio_buffer #(.SIZE(16)) audioBuffer(
+    audio_buffer #(.SIZE(8)) audioBuffer(
         clk_48khz, 
         reset, 
         sd_ready, 
@@ -149,7 +148,7 @@ playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
         audio_sample, 
         audio_interface.receiver
     );
-    pwm #(11) audioOutput(CLK100MHZ, reset, clk_48khz, audio_sample, AUD_PWM);
+    pwm #(8) audioOutput(CLK100MHZ, reset, clk_48khz, audio_sample, AUD_PWM);
 
 `endif
 

design/sd/read_data.sv

@@ -9,7 +9,6 @@
  ***/
 module read_data(
     input clk,
-    input mem_clk,
     input reset,
     input [3:0] sd_data,
     audio_buffer_interface.driver buffer

design/sd/sd_controller.sv

@@ -12,7 +12,6 @@ module sd_controller(
 (* MARK_DEBUG = "TRUE" *)
     input logic fast_clk,
     input logic crc_clk,
-    input logic mem_clk,
     input logic reset,
 (* MARK_DEBUG = "TRUE" *)
     input logic [3:0] sd_data,
@@ -105,7 +104,6 @@ read_command slowReader(
 // The data line is only ever used at fast_clk speeds
 read_data dataHandler(
     fast_clk,
-    mem_clk,
     reset,
     sd_data,
     buffer