157 lines
4.1 KiB
Systemverilog
157 lines
4.1 KiB
Systemverilog
/***
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* nexys_a7_top.sv - top level design module specific to Nexys A7100T.
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*
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* @author: Waylon Cude, Dilanthi Prentice
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* @date: 6/12/2025
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*
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* **/
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`ifdef VERILATOR
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`include "sdvd_defs.sv"
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`endif
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import sdvd_defs::SPEED;
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module nexys_a7_top(
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input logic CLK100MHZ, CPU_RESETN,
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input logic BTNC, BTNR,
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output logic AUD_PWM, AUD_SD,
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output logic CA,CB,CC,CD,CE,CF,CG,
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output logic [7:0] AN,
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output wire LED[0:0],
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output wire SD_RESET,SD_SCK,
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inout wire [3:0] SD_DAT,
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inout wire SD_CMD,
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input wire SD_CD
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);
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// Active high reset
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wire reset;
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assign reset = ~CPU_RESETN;
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logic clk_1khz, clk_10hz;
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logic clk_48khz, clk_1mhz;
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logic seconds_pulse;
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SPEED speed;
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audio_buffer_interface audio_interface();
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// Map C{A-G} to an array of 7-segment displays
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wire [6:0] segments [7:0];
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wire [2:0] segment_mux_select;
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// These segments are currently unused
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assign segments[7] = 0;
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assign segments[6] = 0;
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// These are the ones we're using
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assign {CA,CB,CC,CD,CE,CF,CG} = ~segments[segment_mux_select];
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logic [$clog2(60)-1:0] seconds;
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logic [$clog2(60)-1:0] minutes;
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logic [$clog2(60)-1:0] hours;
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logic [15:0] audio_sample;
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logic sd_ready;
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logic playing;
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assign LED[0] = playing;
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assign AUD_SD = playing;
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low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, 'z, clk_10hz, seconds_pulse);
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modular_clock_gen #(100_000) anodeClock(CLK100MHZ, reset, clk_1khz);
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// Create a clock with a divisor of 2083, making ~48khz
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modular_clock_gen #(2083) audioClock(CLK100MHZ, reset, clk_48khz);
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modular_clock_gen #(100) pwmClock(CLK100MHZ, reset, clk_1mhz);
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// Count the number on seconds, hours, and minutes elapsed
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// If the speed is faster this will pulse more often than once a second
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// but will still theoretically be a second of video time
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always_ff @(posedge seconds_pulse or posedge reset) begin
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if (reset) begin
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seconds <= 0;
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minutes <= 0;
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hours <= 0;
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end
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else if (seconds == 59) begin
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seconds <= 0;
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if (minutes == 59) begin
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minutes <= 0;
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hours <= hours + 1;
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end
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else
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minutes <= minutes + 1;
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end
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else
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seconds <= seconds + 1;
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end
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display_anode_driver anodeDriver(clk_1khz,reset,AN,segment_mux_select);
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sixty_display secondsSegment (seconds, segments[1], segments[0]);
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sixty_display minutesSegment (minutes, segments[3], segments[2]);
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sixty_display hoursSegment (hours, segments[5], segments[4]);
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// Run the playback speed state machine at a lower rate
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// Gets rid of button bouncing
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playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
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`ifdef ROM
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rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
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assign {SD_RESET,SD_DAT,SD_CMD,SD_SCK} = 'z;
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audio_buffer audioBuffer(
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clk_48khz,
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reset,
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sd_ready,
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'0, // stop signal not used right now
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speed,
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playing,
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audio_sample,
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audio_interface.receiver
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);
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pwm audioOutput(CLK100MHZ, reset, clk_48khz, audio_sample, AUD_PWM);
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`else
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// Power the sd slot
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assign SD_RESET = 0;
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// We don't use more than one dat line
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logic clk_100khz;
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logic clk_25mhz;
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// We can clock this at around 200khz before things start breaking
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// Even at 200khz sometimes things break
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modular_clock_gen #(500) slowSdClock(CLK100MHZ, reset, clk_100khz);
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// Try clocking this slower than max speed
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// To see if that makes it actually work
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//
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// NOTE: It did not make it work
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modular_clock_gen #(400) fastSdClock(CLK100MHZ, reset, clk_25mhz);
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sd_controller realSdPlayer(
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clk_100khz,
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clk_25mhz,
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CLK100MHZ,
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reset,
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SD_DAT,
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SD_CMD,
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sd_ready,
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SD_SCK,
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audio_interface.driver
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);
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audio_buffer #(.SIZE(8)) audioBuffer(
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clk_48khz,
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reset,
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sd_ready,
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'0, // stop signal not used right now
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speed,
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playing,
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audio_sample,
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audio_interface.receiver
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);
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pwm #(8) audioOutput(CLK100MHZ, reset, clk_48khz, audio_sample, AUD_PWM);
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`endif
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endmodule
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