How tf did it break bro
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@@ -17,11 +17,15 @@ module display_anode_driver(
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output logic [7:0] AN,
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output logic [2:0] mux_select);
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// Initialize this once, it can be free-running after
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logic started;
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// This is just a shift register that drives each anode individually
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always_ff @(posedge clk) begin
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if (reset) begin
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AN <= '1 - 1;
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mux_select <= 0;
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started <= 1;
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end
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else begin
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AN <= {AN[6:0], AN[7]};
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