Broken SD card

How tf did it break bro

design/modular_clock_gen.sv

@@ -6,14 +6,20 @@ parameter DIVISOR;
 
 logic [$clog2(DIVISOR)-1:0] counter;
 
+logic set;
+
 // clock will be high for about half of the cycle, depending on integer
 // rounding
 // OOPS this makes it combinational
 //assign oclk = counter < (DIVISOR/2);
 
 always_ff @(posedge clk) begin
-    if (reset)
+    // modular clock has to keep ticking through reset
+    // so everything with a synchronous reset actually works
+    if (reset && !set) begin
         counter <= DIVISOR-1;
+        set <= 1;
+    end
     else if (counter == 0)
         counter <= DIVISOR-1;
     else 

design/nexys_a7_top.sv

@@ -15,7 +15,11 @@ module nexys_a7_top(
     output logic AUD_PWM, AUD_SD,
     output logic CA,CB,CC,CD,CE,CF,CG,
     output logic [7:0] AN,
-    output wire LED[0:0]
+    output wire LED[0:0],
+    output wire SD_RESET,SD_SCK,
+    inout wire [3:0] SD_DAT,
+    inout wire SD_CMD,
+    input wire SD_CD
 );
 
 // Active high reset
@@ -51,7 +55,9 @@ logic playing;
 assign LED[0] = playing;
 assign AUD_SD = playing;
 
-low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
+low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, 'z, clk_10hz, seconds_pulse);
+
+modular_clock_gen #(100_000) anodeClock(CLK100MHZ, reset, clk_1khz);
 
 // Create a clock with a divisor of 2083, making ~48khz
 modular_clock_gen #(2083) audioClock(CLK100MHZ, reset, clk_48khz);
@@ -102,7 +108,35 @@ audio_buffer audioBuffer(
     audio_interface.receiver
 );
 
-rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
+`ifdef ROM
+    rom_sd #("even_flow_16.mem") romSdPlayer(clk_1mhz,reset,sd_ready,audio_interface.driver);
+    assign {SD_RESET,SD_DAT,SD_CMD,SD_SCK} = 'z;
+`else
+    // Power the sd slot
+    assign SD_RESET = 0;
+    // We don't use more than one dat line
+    assign SD_DAT[3:1] = 'z;
+    logic clk_100khz;
+    logic clk_25mhz;
+    // Actually 200khz now
+    // 200khz is slightly unstable??????
+    modular_clock_gen #(1000) slowSdClock(CLK100MHZ, reset, clk_100khz);
+    // Try clocking this slower than max speed
+    // To see if that makes it actually work ...
+    modular_clock_gen #(1000) fastSdClock(CLK100MHZ, reset, clk_25mhz);
+    sd_controller realSdPlayer(
+        clk_100khz,
+        clk_25mhz,
+        CLK100MHZ,
+        reset,
+        SD_DAT[0],
+        SD_CMD,
+        sd_ready,
+        SD_SCK,
+        audio_interface.driver
+    );
+
+`endif
 
 
 endmodule

design/sd/read_command.sv

@@ -9,14 +9,21 @@ module read_command(
     // This has to be large enough to capture each possible response
     output logic [135:0] out_data
 );
+
 enum logic [2:0] {IDLE,START,LISTEN,RECEIVING,DONE} state, next_state;
 
 // This should be large enough to capture the largest 136-bit response
 logic [$clog2(136):0] counter;
 logic [135:0] data_reg;
+logic received_reg;
 
 logic [2:0] response_type_reg;
 
+// oops this was set a cycle before the data was actually ready
+// and if it's just a reg it holds for too long
+// use both for maximum reactivity
+assign received = received_reg && !listen;
+
 always_comb begin
     case (state)
         IDLE:
@@ -54,7 +61,8 @@ always_ff @(posedge clk) begin
     case (state)
         IDLE:
         begin
-            received <= 0;
+            // This defaulted to 1 ... oops
+            received_reg <= 0;
             out_data <= 0;
             if (listen)
                 response_type_reg <= response_type;
@@ -62,11 +70,12 @@ always_ff @(posedge clk) begin
 
         START:
         begin
+            received_reg <= 0;
             // off-by-one/cycle timing issues accumulated to a counter offset
             // of 3.
-            counter <= get_bits(response_type_reg) - 3;
+            // 3 in simulation, 2 in reality????
+            counter <= get_bits(response_type_reg) - 2;
             data_reg <= 0;
-            received <= 0;
         end
 
         LISTEN: 
@@ -83,10 +92,12 @@ always_ff @(posedge clk) begin
 
         DONE:
         begin
-            received <= 1;
             out_data <= data_reg;
-            if (listen)
+            received_reg <= 1;
+            if (listen) begin
+                received_reg <= 0;
                 response_type_reg <= response_type;
+            end
         end
 
         default: ;

design/sd/read_data.sv

@@ -5,6 +5,7 @@ module read_data(
     input clk,
     input reset,
     input sd_data,
+    (* MARK_DEBUG = "TRUE" *)
     audio_buffer_interface.driver buffer
 );
 //  Block data is a start bit, 512 bytes sent msb first, then a CRC16 and end

design/sd/sd_controller.sv

@@ -0,0 +1,391 @@
+/****
+ * sd_controller.sv - Initializes and reads data off an sd card, feeding it
+ *                    into the audio buffer
+ *
+ * @author: Waylon Cude, Dilanthi Prentice
+ * @date: 6/12/25
+ *
+ * **/
+module sd_controller(
+(* MARK_DEBUG = "TRUE" *)
+    input logic slow_clk,
+(* MARK_DEBUG = "TRUE" *)
+    input logic fast_clk,
+    input logic crc_clk,
+    input logic reset,
+(* MARK_DEBUG = "TRUE" *)
+    input logic sd_data,
+    inout logic sd_cmd,
+    output logic ready,
+    output wire clk,
+
+    audio_buffer_interface.driver buffer
+);
+// NOTE: this gets encoded as one-hot, even if in here I set it as a logic[5:0]
+(* MARK_DEBUG = "TRUE" *)
+enum logic [5:0] {
+    INIT,WAIT,SEND_CMD0,WAIT_CMD0,DELAY_CMD0, // last 4
+    SEND_CMD8,WAIT_CMD8,LISTEN_RESPONSE_CMD8,WAIT_RESPONSE_CMD8, // last 8
+    SEND_CMD55,WAIT_CMD55,LISTEN_RESPONSE_CMD55,WAIT_RESPONSE_CMD55, // last 12
+    SEND_ACMD41,WAIT_ACMD41,LISTEN_RESPONSE_ACMD41,WAIT_RESPONSE_ACMD41,ACMD41_DELAY, //17
+    SEND_CMD2,WAIT_CMD2,LISTEN_RESPONSE_CMD2,WAIT_RESPONSE_CMD2, //21
+    SEND_CMD3,WAIT_CMD3,LISTEN_RESPONSE_CMD3,WAIT_RESPONSE_CMD3, //25
+    SEND_CMD7,WAIT_CMD7,LISTEN_RESPONSE_CMD7,WAIT_RESPONSE_CMD7, //29
+    READY_TO_TRANSMIT,
+    TRANSMIT,WAIT_TRANSMIT,WAIT_END,FINISH_TRANSMIT,
+    TRANSMIT2,WAIT_TRANSMIT2,WAIT_END2,FINISH_TRANSMIT2,
+    WAIT_FOR_BUFFER
+    } state, next_state;
+
+(* MARK_DEBUG = "TRUE" *)
+logic fast_clk_enable;
+assign clk = fast_clk_enable ? fast_clk : slow_clk;
+
+logic [$clog2(4114):0] counter;
+logic sd_buffer_half;
+logic [31:0] address;
+
+(* MARK_DEBUG = "TRUE" *)
+logic send_command_start;//, send_command_start_fast;
+(* MARK_DEBUG = "TRUE" *)
+logic [5:0] cmd;
+(* MARK_DEBUG = "TRUE" *)
+logic [31:0] arg;
+(* MARK_DEBUG = "TRUE" *)
+wire send_command_ready;//, send_command_ready_fast;
+
+(* MARK_DEBUG = "TRUE" *)
+logic stored_sd_cmd;
+
+// This needs to swap speeds
+send_command slowSender(
+    clk,
+    crc_clk,
+    reset,
+    send_command_start,
+    cmd,
+    arg,
+    send_command_ready,
+    sd_cmd);
+
+//send_command fastSender(
+//    fast_clk,
+//    crc_clk,
+//    reset,
+//    send_command_start_fast,
+//    cmd,
+//    arg,
+//    send_command_ready_fast,
+//    sd_cmd);
+
+(* MARK_DEBUG = "TRUE" *)
+logic read_command_listen;
+logic [2:0] response_type;
+(* MARK_DEBUG = "TRUE" *)
+wire read_command_received;
+wire [135:0] out_data;
+
+// Hopefully this doesn't get optimized out...
+(* MARK_DEBUG = "TRUE" *)
+logic [47:0] received_data;
+assign received_data = out_data[47:0];
+
+// This doesn't need to swap speeds as we ignore responses to CMD17
+read_command slowReader(
+    slow_clk,
+    reset,
+    read_command_listen,
+    response_type,
+    sd_cmd,
+    read_command_received,
+    out_data
+);
+
+// The data line is only ever used at fast_clk speeds
+read_data dataHandler(
+    fast_clk,
+    reset,
+    sd_data,
+    buffer
+);
+
+//always_ff @(posedge crc_clk) begin
+//    stored_sd_cmd <= sd_cmd;
+//end
+
+// Next state logic
+always_comb begin
+    case (state)
+        INIT: next_state=WAIT;
+        WAIT: 
+            if (counter==0)
+                next_state=SEND_CMD0;
+            else
+                next_state=WAIT;
+        SEND_CMD0:
+            next_state=WAIT_CMD0;
+        WAIT_CMD0:
+            if (send_command_ready)
+                next_state=DELAY_CMD0;
+            else
+                next_state=WAIT_CMD0;
+        DELAY_CMD0:
+            if (counter == 0)
+                next_state=SEND_CMD8;
+            else
+                next_state=DELAY_CMD0;
+        // These state transitions are all very similar, this probably could
+        // be a macro
+        SEND_CMD8:
+            next_state=WAIT_CMD8;
+        WAIT_CMD8:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD8;
+            else
+                next_state=WAIT_CMD8;
+        LISTEN_RESPONSE_CMD8:
+            next_state=WAIT_RESPONSE_CMD8;
+        WAIT_RESPONSE_CMD8:
+            if (read_command_received)
+                next_state=SEND_CMD55;
+            else
+                next_state=WAIT_RESPONSE_CMD8;
+        SEND_CMD2:
+            next_state=WAIT_CMD2;
+        WAIT_CMD2:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD2;
+            else
+                next_state=WAIT_CMD2;
+        LISTEN_RESPONSE_CMD2:
+            next_state=WAIT_RESPONSE_CMD2;
+        WAIT_RESPONSE_CMD2:
+            if (read_command_received)
+                next_state=SEND_CMD3;
+            else
+                next_state=WAIT_RESPONSE_CMD2;
+        SEND_CMD3:
+            next_state=WAIT_CMD3;
+        WAIT_CMD3:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD3;
+            else
+                next_state=WAIT_CMD3;
+        LISTEN_RESPONSE_CMD3:
+            next_state=WAIT_RESPONSE_CMD3;
+        WAIT_RESPONSE_CMD3:
+            if (read_command_received)
+                next_state=SEND_CMD7;
+            else
+                next_state=WAIT_RESPONSE_CMD3;
+        SEND_CMD7:
+            next_state=WAIT_CMD7;
+        WAIT_CMD7:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD7;
+            else
+                next_state=WAIT_CMD7;
+        LISTEN_RESPONSE_CMD7:
+            next_state=WAIT_RESPONSE_CMD7;
+        WAIT_RESPONSE_CMD7:
+            if (read_command_received)
+                next_state=READY_TO_TRANSMIT;
+            else
+                next_state=WAIT_RESPONSE_CMD7;
+
+        
+        SEND_CMD55:
+            next_state=WAIT_CMD55;
+        WAIT_CMD55:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_CMD55;
+            else
+                next_state=WAIT_CMD55;
+        LISTEN_RESPONSE_CMD55:
+            next_state=WAIT_RESPONSE_CMD55;
+        WAIT_RESPONSE_CMD55:
+            if (read_command_received)
+                next_state=SEND_ACMD41;
+            else
+                next_state=WAIT_RESPONSE_CMD55;
+        SEND_ACMD41:
+            next_state=WAIT_ACMD41;
+        WAIT_ACMD41:
+            if (send_command_ready)
+                next_state=LISTEN_RESPONSE_ACMD41;
+            else
+                next_state=WAIT_ACMD41;
+        LISTEN_RESPONSE_ACMD41:
+            next_state=WAIT_RESPONSE_ACMD41;
+        WAIT_RESPONSE_ACMD41:
+            if (read_command_received && !out_data[39])
+                next_state=ACMD41_DELAY;
+            else if (read_command_received && out_data[39])
+                next_state=SEND_CMD2;
+            else
+                next_state=WAIT_RESPONSE_ACMD41;
+        ACMD41_DELAY:
+            if (counter == 0)
+                next_state=SEND_CMD55;
+            else
+                next_state=ACMD41_DELAY;
+
+        READY_TO_TRANSMIT:
+            next_state=TRANSMIT;
+        TRANSMIT:
+            next_state=WAIT_TRANSMIT;
+        WAIT_TRANSMIT:
+            if (sd_data==0)
+                next_state=WAIT_END;
+            else
+                next_state=WAIT_TRANSMIT;
+        WAIT_END:
+            if (counter==0)
+                next_state=FINISH_TRANSMIT;
+            else
+                next_state=WAIT_END;
+        FINISH_TRANSMIT:
+            next_state=TRANSMIT2;
+        TRANSMIT2:
+            next_state=WAIT_TRANSMIT2;
+        WAIT_TRANSMIT2:
+            if (sd_data==0)
+                next_state=WAIT_END2;
+            else
+                next_state=WAIT_TRANSMIT2;
+        WAIT_END2:
+            if (counter==0)
+                next_state=FINISH_TRANSMIT2;
+            else
+                next_state=WAIT_END2;
+        FINISH_TRANSMIT2:
+            next_state=WAIT_FOR_BUFFER;
+
+        WAIT_FOR_BUFFER:
+            if (sd_buffer_half==buffer.address_half)
+                next_state=WAIT_FOR_BUFFER;
+            else
+                next_state=TRANSMIT;
+        default:
+            next_state=INIT;
+    endcase
+
+end
+// This could mostly swap speeds ... however detecting the data line going low
+// would not work
+always_ff @(posedge clk) begin
+    stored_sd_cmd <= sd_cmd;
+    // Transition states
+    if (reset)
+        state <= INIT;
+    else
+        state <= next_state;
+
+    // Sequential outputs/logic
+    case (state)
+        INIT: begin
+            counter <= 80;
+            fast_clk_enable <= 0;
+        end
+        SEND_CMD0: begin
+            cmd<=0;
+            arg<=0;
+            send_command_start <= 1;
+        end
+        WAIT_CMD0: begin
+            counter<=20;
+            send_command_start<=0;
+        end
+        SEND_CMD8: begin
+            cmd <=8;
+            arg <='h1AA;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD8: begin
+            response_type <= 7;
+            read_command_listen <= 1;
+        end
+        SEND_CMD55: begin
+            cmd <= 55;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD55: begin
+            response_type <= 1;
+            read_command_listen <= 1;
+        end
+        SEND_ACMD41: begin
+            cmd <= 41;
+            arg <= 'h40100000;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_ACMD41: begin
+            response_type <= 3;
+            read_command_listen <= 1;
+        end
+        WAIT_RESPONSE_ACMD41: begin
+            read_command_listen<=0;
+            counter<=100;
+        end
+        SEND_CMD2: begin
+            cmd <= 2;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD2: begin
+            response_type <= 2;
+            read_command_listen <= 1;
+        end
+        SEND_CMD3: begin
+            cmd <= 3;
+            arg <= 0;
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD3: begin
+            response_type <= 6;
+            read_command_listen <= 1;
+        end
+        SEND_CMD7: begin
+            cmd <= 7;
+            arg <= {out_data[39:24],16'h0000};
+            send_command_start <=1;
+        end
+        LISTEN_RESPONSE_CMD7: begin
+            response_type <= 1;
+            read_command_listen <= 1;
+        end
+        READY_TO_TRANSMIT: begin
+            fast_clk_enable <= 1;
+            address <= 0;
+            sd_buffer_half <= 0;
+        end
+        TRANSMIT, TRANSMIT2: begin
+            cmd <= 17;
+            arg <= address;
+            send_command_start <= 1;
+        end
+        WAIT_TRANSMIT, WAIT_TRANSMIT2: begin
+            send_command_start <= 0;
+            counter <= 411;
+        end
+        FINISH_TRANSMIT:
+            address <= address +1;
+        FINISH_TRANSMIT2: begin
+            address <= address +1;
+            sd_buffer_half <= ~sd_buffer_half;
+        end
+        WAIT_FOR_BUFFER:
+            ready <= 1;
+        // The logic is simple enough in these to group them
+        WAIT, DELAY_CMD0, ACMD41_DELAY, WAIT_END, WAIT_END2:
+            counter <= counter - 1;
+        WAIT_CMD8,WAIT_CMD55,WAIT_ACMD41,WAIT_CMD2,WAIT_CMD3,WAIT_CMD7:
+            send_command_start<=0;
+        WAIT_RESPONSE_CMD8,WAIT_RESPONSE_CMD55,WAIT_RESPONSE_CMD2,WAIT_RESPONSE_CMD3,
+        WAIT_RESPONSE_CMD7:
+            read_command_listen<=0;
+        default: ;
+
+    endcase
+end
+endmodule

design/sd/send_command.sv

@@ -7,9 +7,9 @@ module send_command(
     input [5:0] command,
     input [31:0] arguments,
     output logic ready,
-    output logic sd_cmd
+    output wire sd_cmd
 );
-
+(* MARK_DEBUG = "TRUE" *)
 logic [47:0] to_send;
 
 logic crc_start;
@@ -18,6 +18,7 @@ logic [6:0] crc;
 
 logic [$clog2(48):0] counter;
 
+(* MARK_DEBUG = "TRUE" *)
 logic send_sd_cmd;
 
 enum logic [2:0] {READY, SEND_CRC, DELAY, WAIT_CRC, SEND_DATA} cur_state, next_state;
@@ -45,7 +46,7 @@ always_comb begin
             else
                 next_state = WAIT_CRC;
         SEND_DATA:
-            if (counter != 0)
+            if (counter != 1)
                 next_state = SEND_DATA;
             else
                 next_state = READY;
@@ -56,7 +57,9 @@ always_comb begin
 end
 
 assign sd_cmd = send_sd_cmd ? 'z : 0;
-assign ready = (cur_state == READY);
+// BUG SPOTTED: Too slow, make the output more reactive
+//              Added start input check to achieve this
+assign ready = (cur_state == READY && !start);
 // Sequential logic
 always_ff @(posedge clk) begin
     // Default to high-z
@@ -92,7 +95,6 @@ end
 always_ff @(posedge clk) begin
     if (reset) begin
         cur_state <= READY;
-        counter <= 48;
     end
     else begin
         cur_state <= next_state;

design/segment_display/display_anode_driver.sv

@@ -17,11 +17,15 @@ module display_anode_driver(
     output logic [7:0] AN, 
     output logic [2:0] mux_select);
 
+// Initialize this once, it can be free-running after
+logic started;
+
 // This is just a shift register that drives each anode individually
 always_ff @(posedge clk) begin
     if (reset) begin
         AN <= '1 - 1;
         mux_select <= 0;
+        started <= 1;
     end
     else begin
         AN <= {AN[6:0], AN[7]};