Demo commit

The audio output is still messed up, but this commit gets everything as
ready as it can get. Fixed up all the testbenches and added state
machines for everything

verification/sd/read_data_tb.sv

@@ -16,7 +16,7 @@ module read_data_tb;
     // A 16-bit audio sample to output
     logic [15:0] sample;
 
-    logic sd_data;
+    logic [3:0] sd_data;
 
     audio_buffer_interface bufferInterface(); 
 
@@ -104,37 +104,41 @@ module read_data_tb;
     end
     task automatic write_random_sd(int start);
         @(posedge sd_clk);
-        sd_data = 1;
+        sd_data = '1;
         // send start bit
         @(posedge sd_clk);
         // send 256 data bits
         sd_data = 0;
         for (int i = 0; i < 256; i++) begin
-            write_byte(test_memory[start+i][7:0]);
-            write_byte(test_memory[start+i][15:8]);
+            write_byte(test_memory[start-i-1][7:0]);
+            write_byte(test_memory[start-i-1][15:8]);
         end
         // Simulate randomized crc bits and stop bit
-        repeat (16) @(posedge sd_clk) sd_data=$urandom;
-        @(posedge sd_clk) sd_data=1;
+        repeat (16*4) @(posedge sd_clk) sd_data=$urandom;
+        @(posedge sd_clk) sd_data='1;
     endtask
     task automatic write_linear_sd(int start);
         @(posedge sd_clk);
-        sd_data = 1;
+        sd_data = '1;
         // send start bit
         @(posedge sd_clk);
         // send 256 data bits
         sd_data = 0;
+        start += 256;
         for (int i = 0; i < 256; i++) begin
+            // NOTE: These are in the wrong order??
+            //       One of the weird cases where simulation is different
+            //       than hardware
             write_byte(start[7:0]);
             write_byte(start[15:8]);
-            start = start+1;
+            start = start-1;
         end
         // Simulate crc bits and stop bit
-        repeat (17) @(posedge sd_clk) sd_data=1;
+        repeat (16*4+1) @(posedge sd_clk) sd_data='1;
     endtask
     task automatic write_byte(logic [7:0] b);
-        for (int i=0; i<8; i++)
-            @(posedge sd_clk) sd_data=b[7-i];
+        @(posedge sd_clk) sd_data=b[7:4];
+        @(posedge sd_clk) sd_data=b[3:0];
     endtask
 
 endmodule

verification/sd/send_command_tb.sv

@@ -40,6 +40,7 @@ initial begin
     counter = 48;
 
     @(posedge clk);
+    start = 0;
 
     // Try receiving the CMD8
     while (counter != 0) begin
@@ -54,9 +55,11 @@ initial begin
     assert (fill_me === {2'b01, 6'd8, 32'h1AA, 8'h87})
         else $error("Received wrong command, got 0x%x",fill_me);
 
+    repeat (1) @(posedge clk);
     assert (ready)
         else $error("SD command sender not ready");
 
+    repeat (10) @(posedge clk);
 
     $finish;
 end