Added command signal driver module

2025-06-06 20:49:18 -07:00
parent 71f08bdf15
commit e32563131f
4 changed files with 188 additions and 6 deletions
@@ -26,3 +26,7 @@
 - clocked too slow
 - initial goal of 16-bit audio isn't feasible because 100MHz isn't fast enough
  to pwm based on a 16-bit counter, would give a sample rate of 1.5khz
+
+### command_sender
+- output ready signal was delay a cycle because it was set by sequential logic,
+  detected in testing, changed it to a combinational output for 1 cycle speedup