added pwn.sv

added x16 fast forward speed to playback_controller.sv

corrected dates on pwn.sv, playback_controller.sv, display_converter.sv,
and seconds_display.sv

design/audio/pwm.sv

@@ -1,3 +1,11 @@
+/****
+ * pwm.sv - [must edit in future]
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: [not sure when due yet]
+ *
+ *
+ * */
 module pwm(
     input logic clk, reset,
     // Load control signal, if this is high we should load a new sample
@@ -8,25 +16,33 @@ module pwm(
     output wire pwm_pin
 );
 
-// What I imagine is that the counter here can be incremented each clock.
-// If the counter value is less than or equal to the value in the sample buffer
-// then you should turn on the PWM output. Otherwise if the counter is greater
-// than the value in the sample buffer the output will be off.
-//
-// This means that for small sample values the output will be enabled for only
-// short periods of time, exactly what we want.
 logic [15:0] pulse_counter;
-
-// A buffer to hold the sample in. Every clock cycle you should check load
-// to see if you should pull the sample off the bus and store it in here.
 logic [15:0] sample_buffer;
-
-// A control signal for driving the PWM high or low. This gets translated into
-// either a 'z or a '0 later as the PWM requires.
 logic should_output;
 
-// NOTE: tristating the pwm pin with a 'z will output a 1
-//       sending a 0 will pull the pin to 0 as usual
+always_ff @(posedge clk)
+begin
+    if (reset)
+    begin
+        pulse_counter <= 0;
+        sample_buffer <= 0;
+    end
+    
+    else
+    begin
+        if (load)
+            sample_buffer <= sample;
+        
+        pulse_counter <= pulse_counter + 1;
+
+        if (pulse_counter < sample_buffer)
+            should_output <= 1;
+        else
+            should_output <= 0;
+    end
+
+end
+
 assign pwm_pin = should_output ? 'z : '0;