Lots of changes, trying to get ROM working

I think I did some funny math errors so new goal is 8-bit pcm

verification/audio/pwm_tb.sv

@@ -0,0 +1,57 @@
+/*****
+ * pwm_tb.sv - testbench for the pwm.sv module. 
+ *
+ * @author: Dilanthi Prentice, Waylon Cude
+ * @date: 6/12/2025
+ * */
+
+module pwm_tb;
+    bit clk, reset;
+
+    logic load;
+    wire pwm_pin;
+    logic [15:0] sample;
+
+    pwm dut (.*);
+
+    initial forever #10 clk = ~clk;
+
+    initial begin
+        reset = 1;
+        @(posedge clk);
+        @(posedge clk);
+        reset = 0;
+        load = 1;
+        sample = 0;
+        for (int i=0; i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 0)
+                else $error("Should be low at %d",i);
+        end
+        reset = 0;
+        load = 1;
+        sample = '1;
+        @(posedge clk)
+        for (int i=0; i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 'z)
+                else $error("Should be high at %d",i);
+        end
+
+        reset = 0;
+        load = 1;
+        // Should be about half on
+        sample = 1<<15;
+        @(posedge clk)
+        for (int i=0; i < (1<<15); i++) begin
+            @(posedge clk) assert (pwm_pin === 'z) 
+                else $error("Should be high at %d",i);
+        end
+        sample = 1<<15;
+        for (int i = (1  << 15); i < (1<<16)-1; i++) begin
+            @(posedge clk) assert (pwm_pin === 0)
+                else $error("Should be low at %d",i);
+        end
+        $finish;
+
+    end
+
+endmodule

verification/audio/pwn_tb.sv

@@ -1,6 +0,0 @@
-/*****
- * pwn_tb.sv - testbench for the pwn.sv module. 
- *
- * @author: Dilanthi Prentice, Waylon Cude
- * @date: 6/12/2025
- * */

verification/sd/rom_sd_tb.sv

@@ -0,0 +1,155 @@
+`ifdef VERILATOR
+    `include "sdvd_defs.sv"
+`endif
+
+module rom_sd_tb;
+    bit clk,reset;
+    wire ready;
+    int errors;
+    logic [10:0] i;
+
+    audio_buffer_interface buffer();
+
+    rom_sd #("consecutive.mem") dut (clk,reset,ready,buffer.driver);
+
+
+    initial forever #10 clk = ~clk;
+
+    initial begin
+        reset = 1;
+        buffer.address_half = 0;
+        @(posedge clk);
+        reset = 0;
+        // Audio data should not be flowing yet
+        #1 assert (buffer.dina == 0) 
+        else begin
+            errors++;
+            $error("Data not zero after reset, found 0x%x",buffer.dina);
+        end
+        repeat (3) @(posedge clk);
+        for (i = 0; i < 1024;) begin
+            @(posedge clk);
+            #1
+
+            assert (buffer.addra === i)
+            else begin 
+                errors++;
+                $error("Incorrect address, expected %x found %x",i,buffer.addra);
+            end
+
+            assert (buffer.dina === ((i + 1) % 256))
+            else begin 
+                errors++;
+                $error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
+            end
+
+            assert (i == 0 || buffer.ena === 1)
+            else begin 
+                $error("Enable not high");
+                errors++;
+            end
+
+            assert (buffer.address_half == 0)
+            else begin 
+                errors++;
+                $error("Incorrect address half, expected 0 but found %d",buffer.address_half);
+            end
+
+            i = i + 1;
+        end
+        // Wait a cycle for the buffer to catch up
+        @(posedge clk);
+        // Make sure that we start waiting and that we signal that the buffer
+        // is ready
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after first full cycle");
+        end
+        assert(ready === 1)
+        else begin
+            errors++;
+            $error("Buffer did not signal ready");
+        end
+
+        assert(dut.buffer_half === 1)
+        else begin
+            errors++;
+            $error("Buffer half did not correctly change to 1");
+        end
+
+        // Set the address half high so we can test waiting/catching up to the
+        // buffer
+        buffer.address_half = 1;
+        repeat (100) @(posedge clk);
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after first full cycle");
+        end
+
+        buffer.address_half = 0;
+        repeat (3) @(posedge clk);
+        // Check that sending into the upper half of the buffer works as
+        // expected
+        while (i != 0) begin
+            @(posedge clk);
+            #1
+
+            assert (buffer.addra === i)
+            else begin 
+                errors++;
+                $error("Incorrect address, expected %x found %x",i,buffer.addra);
+            end
+
+            assert (buffer.dina === ((i + 1) % 256))
+            else begin 
+                errors++;
+                $error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
+            end
+
+            assert (i == 0 || buffer.ena === 1)
+            else begin 
+                $error("Enable not high");
+                errors++;
+            end
+
+            assert (buffer.address_half == 0)
+            else begin 
+                errors++;
+                $error("Incorrect address half, expected 0 but found %d",buffer.address_half);
+            end
+
+            i = i + 1;
+        end
+
+        // Wait a cycle for the buffer to catch up
+        @(posedge clk);
+        // Make sure that we start waiting
+        #1 assert(buffer.ena === 0)
+        else begin
+            errors++;
+            $error("Buffer did not wait after second full cycle");
+        end
+        assert(ready === 1)
+        else begin
+            errors++;
+            $error("Buffer did not signal ready");
+        end
+
+        assert(dut.buffer_half === 0)
+        else begin
+            errors++;
+            $error("Buffer half did not correctly change to 0");
+        end
+
+
+        $display("Found %0d errors while testing rom_sd",errors);
+
+        $finish;
+
+
+
+    end
+
+endmodule

verification/waveform_configs/rom_sd_waveform.wcfg

@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="rom_sd_tb_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="rom_sd_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+      <ZoomEndTime time="143.201 ns"></ZoomEndTime>
+      <Cursor1Time time="0.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="453"></NameColumnWidth>
+      <ValueColumnWidth column_width="200"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="10" />
+   <wvobject type="logic" fp_name="/rom_sd_tb/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/reset">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/ready">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/rom_data">
+      <obj_property name="ElementShortName">rom_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rom_data[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/current">
+      <obj_property name="ElementShortName">current[2:0]</obj_property>
+      <obj_property name="ObjectShortName">current[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/dut/rom_addr">
+      <obj_property name="ElementShortName">rom_addr[16:0]</obj_property>
+      <obj_property name="ObjectShortName">rom_addr[16:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/dut/rom_enable">
+      <obj_property name="ElementShortName">rom_enable</obj_property>
+      <obj_property name="ObjectShortName">rom_enable</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/buffer/addra">
+      <obj_property name="ElementShortName">addra[10:0]</obj_property>
+      <obj_property name="ObjectShortName">addra[10:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/rom_sd_tb/buffer/dina">
+      <obj_property name="ElementShortName">dina[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dina[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/rom_sd_tb/buffer/ena">
+      <obj_property name="ElementShortName">ena</obj_property>
+      <obj_property name="ObjectShortName">ena</obj_property>
+   </wvobject>
+</wave_config>