Lots of changes, trying to get ROM working

I think I did some funny math errors so new goal is 8-bit pcm
2025-06-05 18:48:53 -07:00
parent 02e2d77640
commit 7980424dc8
18 changed files with 387489 additions and 134 deletions
@@ -12,3 +12,17 @@

 ### Low Freq Clock Gen
 - Was initially trying to do modulo at max clock speed, failing timing
+
+
+### sd_rom
+- ROM was getting totally optimized out and was doing nothing in simulation, and
+  didn't show up in synthesized design
+- Timing issues, ROM was one cycle slower than expected, latching takes an extra
+  cycle too, had to rework state machines, there are a bonus 2 delay states when
+  starting and ending writes
+
+### PWM
+- major design problems
+- clocked too slow
+- initial goal of 16-bit audio isn't feasible because 100MHz isn't fast enough
+  to pwm based on a 16-bit counter, would give a sample rate of 1.5khz