Lots of changes, trying to get ROM working

I think I did some funny math errors so new goal is 8-bit pcm

design/audio/audio_buffer.sv

@@ -31,11 +31,6 @@ module audio_buffer(
     // Inputs for the memory buffer
     audio_buffer_interface.receiver driver
 );
-
-// Whether the current address being read from is in the upper or lower
-// half of the 2KiB buffer
-let address_half = driver.address_half;
-
 logic [9:0] address;
 
 // State register
@@ -45,8 +40,11 @@ logic [15:0] doutb;
 // A single bit counter, to avoid feeding samples given the 1 cycle read delay
 logic delay;
 
+// Whether the current address being read from is in the upper or lower
+// half of the 2KiB buffer
+//
 // The MSB of the address == higher/lower half address
-assign address_half = address[9];
+assign driver.address_half = address[9];
 
 always_ff @(posedge clk) begin
     enb <= 0;
@@ -143,12 +141,18 @@ buffer (
   .rstb(reset),            // 1-bit input: Reset signal for the final port B output register stage.
                           // Synchronously resets output port doutb to the value specified by
                           // parameter READ_RESET_VALUE_B.
-  .wea(driver.ena)               // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+  .wea(driver.ena),       // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                           // for port A input data port dina. 1 bit wide when word-wide writes are
                           // used. In byte-wide write configurations, each bit controls the
                           // writing one byte of dina to address addra. For example, to
                           // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                           // is 32, wea would be 4'b0010.
+  // Extra inputs that I guess I need
+  .sleep(0),
+  .injectsbiterra(0),
+  .injectdbiterra(0),
+  // With a latency of 1 this surely does not matter
+  .regceb(enb)
 );
 
 endmodule

design/audio/pwm.sv

@@ -16,8 +16,11 @@ module pwm(
     // The audio output pin
     output wire pwm_pin
 );
+// This  can't be 16 or we are slowing the audio rate down by a factor of
+// 2^5=32
+parameter DEPTH=8;
 
-logic [15:0] pulse_counter;
+logic [DEPTH-1:0] pulse_counter;
 logic [15:0] sample_buffer;
 logic should_output;
 
@@ -27,6 +30,7 @@ begin
     begin
         pulse_counter <= 0;
         sample_buffer <= 0;
+        should_output <= 0;
     end
     
     else
@@ -36,7 +40,7 @@ begin
         
         pulse_counter <= pulse_counter + 1;
 
-        if (pulse_counter < sample_buffer)
+        if (pulse_counter < sample_buffer[15-:DEPTH])
             should_output <= 1;
         else
             should_output <= 0;