Add some stubbed out modules for the first bit
All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
Hopefully theses are right ...
This commit is contained in:
parent
831e588986
commit
34d62a197f
27
SDVD.xpr
27
SDVD.xpr
@ -98,9 +98,24 @@
|
|||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
|
<File Path="$PPRDIR/design/playback_controller.sv">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/design/seconds_display.sv">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="AutoDisabled" Val="1"/>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="Debouncer"/>
|
<Option Name="TopModule" Val="Playback_Controller"/>
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
@ -120,7 +135,7 @@
|
|||||||
<Filter Type="Srcs"/>
|
<Filter Type="Srcs"/>
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="Debouncer"/>
|
<Option Name="TopModule" Val="Playback_Controller"/>
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
@ -167,7 +182,9 @@
|
|||||||
<Runs Version="1" Minor="22">
|
<Runs Version="1" Minor="22">
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
@ -177,7 +194,9 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
<Step Id="opt_design"/>
|
<Step Id="opt_design"/>
|
||||||
<Step Id="power_opt_design"/>
|
<Step Id="power_opt_design"/>
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
//NOTE: you should drive this with a slow clock to actually debounce input
|
//NOTE: you should drive this with a slow clock to actually debounce input
|
||||||
module Debouncer(input logic clk, input reset, input source, output wire out);
|
module debouncer(input logic clk, input reset, input source, output wire out);
|
||||||
|
|
||||||
logic pressed;
|
logic pressed;
|
||||||
assign out = pressed;
|
assign out = pressed;
|
||||||
|
|||||||
20
design/playback_controller.sv
Normal file
20
design/playback_controller.sv
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
module Playback_Controller(
|
||||||
|
// This clock should be reasonably slow
|
||||||
|
input logic clk,
|
||||||
|
input logic reset,
|
||||||
|
|
||||||
|
// Play and pause are the same button
|
||||||
|
input logic play,
|
||||||
|
input logic ff,
|
||||||
|
|
||||||
|
// Output is 0, 1x, 2x, 4x, or 8x
|
||||||
|
output wire [3:0] speed
|
||||||
|
);
|
||||||
|
|
||||||
|
wire play_pulse,ff_pulse;
|
||||||
|
|
||||||
|
// NOTE: These might need to be hooked to an even lower clock? Not sure
|
||||||
|
debouncer playDebouncer (clk,reset,play,play_pulse);
|
||||||
|
debouncer ffDebouncer (clk,reset,ff,ff_pulse);
|
||||||
|
|
||||||
|
endmodule
|
||||||
10
design/seconds_display.sv
Normal file
10
design/seconds_display.sv
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
module seconds_display(
|
||||||
|
input logic clk,
|
||||||
|
input logic reset,
|
||||||
|
input [$clog2(60)-1:0] counter,
|
||||||
|
output [7:0] display_tens,
|
||||||
|
output [7:0] display_ones
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
x
Reference in New Issue
Block a user