Waylon Cude
e32563131f
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64 lines
1.1 KiB
Systemverilog
64 lines
1.1 KiB
Systemverilog
module send_command_tb;
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bit clk;
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// The crc should be clocked way faster than the sender
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bit crc_clk;
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logic reset;
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logic start;
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logic [5:0] command;
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logic [31:0] arguments;
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wire ready;
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wire sd_cmd;
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logic [47:0] fill_me;
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int counter;
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logic sd_cmd_real;
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assign sd_cmd_real = (sd_cmd === 'z) ? 1 : 0;
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send_command dut(.*);
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initial forever #100 clk = ~clk;
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initial forever #20 crc_clk = ~crc_clk;
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initial begin
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reset = 1;
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start = 0;
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repeat (2) @(posedge clk);
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reset = 0;
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@(posedge clk);
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start = 1;
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command = 8;
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arguments = 'h1AA;
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counter = 48;
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@(posedge clk);
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// Try receiving the CMD8
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while (counter != 0) begin
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// Check for the start bit, or that we're receiving a message
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if (sd_cmd_real != 1 || counter != 48) begin
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fill_me = {fill_me[46:0], sd_cmd_real};
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counter--;
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end
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@(posedge clk);
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end
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assert (fill_me === {2'b01, 6'd8, 32'h1AA, 8'h87})
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else $error("Received wrong command, got 0x%x",fill_me);
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assert (ready)
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else $error("SD command sender not ready");
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$finish;
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end
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endmodule
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