Waylon Cude
f840d27b8e
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The audio output is still messed up, but this commit gets everything as ready as it can get. Fixed up all the testbenches and added state machines for everything
70 lines
2.1 KiB
Systemverilog
70 lines
2.1 KiB
Systemverilog
// Whenever we receive a data block, start spitting bytes out into the audio
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// buffer bram. This could always be clocked at the 25MHz default speed clock,
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// or it could switch over like the writer has to
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module read_data(
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input clk,
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input reset,
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input [3:0] sd_data,
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audio_buffer_interface.driver buffer
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);
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// Block data is a start bit, 512 bytes sent msb first, then a CRC16 and end
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// bit.
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// NOTE: This doesn't check which side of the buffer the audio player is
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// reading from, so theoretically it could overwrite audio that's being
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// played. However, as long as the sd card controller doesn't request extra
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// blocks this shouldn't be an issue
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localparam BLOCK_SIZE=512*2+16*4+2;
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logic [$clog2(BLOCK_SIZE):0] counter;
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logic [7:0] byte_shift;
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logic [3:0] byte_counter;
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assign buffer.clka = clk;
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always_ff @(posedge clk) begin
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if (reset) begin
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buffer.ena <= 0;
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// Start negative so adding bytes will get us to the right address
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buffer.addra <= 0 - 512;
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buffer.dina <= 0;
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end
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else begin
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// We ignore the lower 16*4+1 bits of the block
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// CRC is apparently sent on each line, back to back
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if (counter > 16*4) begin
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counter <= counter - 1;
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byte_shift <= {byte_shift[3:0],sd_data};
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byte_counter <= byte_counter - 1;
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// Store received byte in audio buffer and reset counter
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if (byte_counter == 0) begin
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byte_counter <= 1;
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buffer.dina <= {byte_shift[3:0],sd_data};
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buffer.ena <= 1;
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end
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// Turn the enable signal off so we don't accidentally write
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// anything weird
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if (byte_counter == 1) begin
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buffer.addra <= buffer.addra - 1;
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end
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end
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else if (counter != 0) begin
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counter<=counter-1;
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buffer.ena <= 0;
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end
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else if (sd_data == 0) begin
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// In wide bus mode we read bytes in a descending order
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buffer.addra <= buffer.addra + 1024;
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counter <= BLOCK_SIZE;
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byte_counter <= 3;
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end
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end
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end
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endmodule
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